
Rev. 1.00 Sep. 13, 2007 Page xi of xxviii
4.3
Register Descriptions .......................................................................................................... 87
4.3.1
Reset Status Register (RSTSR)........................................................................... 87
4.3.2
Reset Control/Status Register (RSTCSR)........................................................... 88
4.4
Pin Reset ............................................................................................................................. 89
4.5
Deep Software Standby Reset............................................................................................. 89
4.6
Watchdog Timer Reset ....................................................................................................... 89
4.7
Determination of Reset Generation Source......................................................................... 89
Section 5 Exception Handling ...............................................................................91
5.1
Exception Handling Types and Priority.............................................................................. 91
5.2
Exception Sources and Exception Handling Vector Table ................................................. 92
5.3
Reset ................................................................................................................................... 94
5.3.1
Reset Exception Handling................................................................................... 94
5.3.2
Interrupts after Reset........................................................................................... 95
5.3.3
On-Chip Peripheral Functions after Reset Release ............................................. 95
5.4
Traces.................................................................................................................................. 97
5.5
Address Error...................................................................................................................... 98
5.5.1
Address Error Source.......................................................................................... 98
5.5.2
Address Error Exception Handling ..................................................................... 99
5.6
Interrupts........................................................................................................................... 100
5.6.1
Interrupt Sources............................................................................................... 100
5.6.2
Interrupt Exception Handling ........................................................................... 101
5.7
Instruction Exception Handling ........................................................................................ 101
5.7.1
Trap Instruction................................................................................................. 101
5.7.2
Sleep Instruction Exception Handling .............................................................. 102
5.7.3
Exception Handling by Illegal Instruction ........................................................ 103
5.8
Stack Status after Exception Handling.............................................................................. 104
5.9
Usage Note........................................................................................................................ 105
Section 6 Interrupt Controller ..............................................................................107
6.1
Features............................................................................................................................. 107
6.2
Input/Output Pins.............................................................................................................. 109
6.3
Register Descriptions ........................................................................................................ 109
6.3.1
Interrupt Control Register (INTCR) ................................................................. 110
6.3.2
CPU Priority Control Register (CPUPCR) ....................................................... 111
6.3.3
Interrupt Priority Registers A to I, K to O, Q, and R (IPRA to IPRI, IPRK to
IPRO, IPRQ, and IPRR).................................................................................... 112
6.3.4
IRQ Enable Register (IER) ............................................................................... 114
6.3.5
IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................. 116
6.3.6
IRQ Status Register (ISR)................................................................................. 121