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參數(shù)資料
| 型號： | R5F56218BDBG#U0 |
| 廠商： | Renesas Electronics America |
| 文件頁數(shù)： | 75/148頁 |
| 文件大小： | 0K |
| 描述： | MCU 32BIT FLASH 512KROM 176LFBGA |
| 產(chǎn)品培訓(xùn)模塊： | RX Compare Match Timer RX DMAC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | RX600 |
| 核心處理器： | RX |
| 芯體尺寸： | 32-位 |
| 速度： | 100MHz |
| 連通性： | CAN，EBI/EMI，I²C，SCI，SPI，USB |
| 外圍設(shè)備： | DMA，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 126 |
| 程序存儲器容量： | 512KB（512K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 96K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10/12b，D/A 2x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 176-LFBGA |
| 包裝： | 托盤 |
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PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 30
2004 Microchip Technology Inc.
3.1
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR
circuitry, tie the MCLR pin through a 1 k
to 10 k
resistor to VDD. This will eliminate external RC
components usually needed to create a Power-on
Reset delay. A minimum rise rate for VDD is specified
(parameter D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
FIGURE 3-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
3.2
Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in Reset as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable/
disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC
parameter #33 for details.
3.3
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
Sleep.
3.4
PLL Lock Time-out
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to
provide a fixed time-out that is sufficient for the PLL to
lock to the main oscillator frequency. This PLL lock
time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
3.5
Brown-out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A Reset may not occur if VDD falls below
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. If the Power-up Timer is enabled, it will be
invoked after VDD rises above BVDD; it then will keep
the chip in Reset for an additional time delay (parame-
ter #33). If VDD drops below BVDD while the Power-up
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
VDD rises above BVDD, the Power-up Timer will
execute the additional time delay.
3.6
Time-out Sequence
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
power-up.
Since the time-outs occur from the POR pulse, the
time-outs will expire if MCLR is kept low long enough.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXX20 device
operating in parallel.
Table 3-2 shows the Reset conditions for some Special
Function Registers, while Table 3-3 shows the Reset
conditions for all of the registers.
Note 1:
External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2:
R < 40 k
is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3:
R1 = 1 k
to 10 k will limit any current flow-
ing into MCLR from external capacitor C, in
the event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
C
R1
R
D
VDD
MCLR
PIC18FXX20
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