參數(shù)資料
型號(hào): R5F56108WNBG
元件分類(lèi): 微控制器/微處理器
英文描述: 64-BIT, FLASH, MICROCONTROLLER
封裝: LFBGA-176
文件頁(yè)數(shù): 68/85頁(yè)
文件大?。?/td> 1355K
代理商: R5F56108WNBG
RX610 Group
5. Electrical Characteristics
R01DS0097EJ0100
Rev.1.00
Page 70 of 83
Apr 22, 2011
Table 5.8
Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V, PCLK = 8 to 50 MHz
Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications)
Item
Symbol
Min. *
1*2
Max.
Unit
Test
Conditions
SCL input cycle time
tSCL
8(10) x (1/PCLK) + 1300
ns
SCL input high pulse width
tSCLH
3(5) x (1/PCLK) + 300
ns
SCL input low pulse width
tSCLL
5x (1/PCLK) + 1000
ns
SCL, SDA input rising time
tSr
1000
ns
SCL, SDA input falling time
tSf
300
ns
SCL, SDA input spike pulse removal
time
tSP
0
4 x (1/PCLK)
ns
SDA input bus free time
tBUF
5x (1/PCLK) + 1000
ns
Start condition input hold time
tSTAH
3(5) x (1/PCLK) + 300
ns
Re-start condition input setup time
tSTAS
5x (1/PCLK) + 1000
ns
Stop condition input setup time
tSTOS
3(5) x (1/PCLK) + 300
ns
Data input setup time
tSDAS
250
ns
Data input hold time
tSDAH
0
ns
RIIC
(Standard-mode)
ICFER.FMPE = 0
SCL, SDA capacitive load
Cb
400
pF
SCL input cycle time
tSCL
8(10) x (1/PCLK) + 600
ns
SCL input high pulse width
tSCLH
3(5) x (1/PCLK) + 300
ns
SCL input low pulse width
tSCLL
5 x (1/PCLK) + 300
ns
SCL, SDA input rising time
tSr
20 + 0.1Cb
300
ns
SCL, SDA input falling time
tSf
20 + 0.1Cb
300
ns
SCL, SDA input spike pulse removal
time
tSP
0
4 x (1/PCLK)
ns
SDA input bus free time
tBUF
5 x (1/PCLK) + 300
ns
Start condition input hold time
tSTAH
3(5) x (1/PCLK) + 300
ns
Re-start condition input setup time
tSTAS
5 x (1/PCLK) + 300
ns
Stop condition input setup time
tSTOS
3(5) x (1/PCLK) + 300
ns
Data input setup time
tSDAS
100
ns
Data input hold time
tSDAH
0
ns
RIIC
(Fast-mode)
ICFER.FMPE = 0
SCL, SDA capacitive load
Cb
400
pF
Figure 5.25
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