
REVISION HISTORY
Under development Preliminary document
Specifications in this document are tentative and subject to change.
0.90
Aug. 09, 2011
1158
Figure 30.31 Concept of a Frame, added
1159
Figure 30.32 Correspondence between the RSPI Command Register and Transmit/Receive
Buffers in Sequence Operations, added
1163
Figure 30.34 Example of Initialization Flowchart in Master Mode (SPI Operation), changed
1167
Figure 30.37 Example Flowchart for Transfer Operations in Slave Mode (SPI Operation), changed
1169
Figure 30.38 Procedure for Determining the Form of Serial Transmission in Master Mode, changed
1169
Figure 30.39 Concept of a Frame, added
1170
Figure 30.40 Correspondence between the RSPI Command Register and Transmit/Receive
Buffers in Sequence Operations, added
1171
Figure 30.41 Example of Initialization Flowchart in Master Mode (Clock Synchronous Operation),
changed
1172
Figure 30.42 Example Flowchart for Transfer Operations in Master Mode (Clock Synchronous
Operation), changed
1175
Figure 30.44 Example Flowchart for Transfer Operations in Slave Mode (CPHA = 1)
(Clock Synchronous Operation), changed
1178
Figure 30.48 Configuration of Shift Register I/O Paths in Loopback Mode (Master Mode), changed
1180
30.3.17 Interrupt Sources: Description changed
11780
Table 30.14 Interrupt Sources of RSPI, changed
1181,
1182
30.4 Event Link Output: Description changed
1182
30.5.2 Interrupt Handling and Event Linking, added
31. CRC Calculator (CRC)
1185
31.2.1 CRC Control Register (CRCCR): Description changed
1186
31.2.3 CRC Data Output Register (CRCDOR): Description changed
32. 12-Bit A/D Converter (S12AD)
1192
Table 32.1 Specifications of 12-Bit A/D Converter: Note3 added
1238
32.7.7 Allowable Impedance of Signal Source: Description changed
1238
Table 32.10 Specifications of Analog Input Pins, changed
33. D/A Converter
1244
33.2.2 D/A Control Register (DACR): Description changed
33.2.3 DADRm Format Select Register (DADPR): bit name changed
34. Temperature Sensor
1251
34.3.1 Preparation for Using the Temperature Sensor: Description changed
1252
34.3.2 Setting of 12-Bit A/D Converter: Description changed
1252
Table 34.3 A/D Converter Conversion Clock (PCLKD) Frequencies and ADSSTRT Settings,
changed
1253
Figure 34.2 Procedure for Using the Temperature Sensor, changed
35. Comparator A
1255
Figure 35.1 Block Diagram of Comparator A, changed
1258
35.2.1 Voltage Monitoring Circuit/Comparator A Control Register (LVCMPCR):
Description changed
1259,
1260
35.2.2 Voltage Monitoring 1 Circuit/Comparator A1 Control Register 0 (LVD1CR0):
Description changed
1261,
1262
35.2.3 Voltage Monitoring 2 Circuit/Comparator A2 Control Register 0 (LVD2CR0):
Description changed
1263
35.2.4 Voltage Monitoring 1 Circuit/Comparator A1 Control Register 1 (LVD1CR1):
Description changed
1264
35.2.5 Voltage Monitoring 1 Circuit/Comparator A1 Status Register (LVD1SR):
Description changed
1265
35.2.6 Voltage Monitoring 2 Circuit/Comparator A2 Control Register 1 (LVD2CR1):
Description changed
1266
35.2.7 Voltage Monitoring 2 Circuit/Comparator A2 Status Register (LVD2SR):
Description changed
1267
35.3 Monitoring Comparison Results: Description changed
1268
Table 35.4 Procedure for Setting Bits Associated with Comparator A1 Interrupt, changed
1269
Figure 35.2 Operating Example of Comparator A1, changed
1270
Table 35.5 Procedure for Setting Bits Associated with Comparator A2 Interrupt, changed
1271
Figure 35.3 Operating Example of Comparator A2, changed
36. Comparator B
1279
Table 36.4 Procedure for Setting Registers Associated with Comparator B,changed
Rev.
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Description
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Summary