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| 型號： | R5F36S1ENFB |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 32.72 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 35/55頁 |
| 文件大?。?/td> | 748K |
| 代理商： | R5F36S1ENFB |
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M16C/6S1 Group
5. Electrical Characteristics
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0054EJ0050 Rev.0.50
Page 40 of 52
Jun 14, 2011
Notes:
1.
Definition of program and erase cycles
The program and erase cycles refer to the number of per-block erasures.
If the program and erase cycles are n (n = 10,000), each block can be erased n times.
For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this
counts as one program and erase cycles. Data cannot be written to the same address more than once without
erasing the block (rewrite prohibited).
2.
Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3.
In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be
minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the
erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain
data on the erasure cycles of each block and limit the number of erase operations to a certain number.
4.
If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5.
Customers desiring program/erase failure rate information should contact their Renesas technical support
representative.
6.
The data hold time includes time that the power supply is off or the clock is not supplied.
7.
After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the
erase sequence cannot be completed.
Table 5.10
Flash Memory (Data Flash) Electrical Characteristics
VCC1 = 2.7 to 3.6 V at Topr = -20 to 85°C/-40 to 85°C, unless otherwise specified.
Symbol
Parameter
Conditions
Standard
Unit
Min.
Typ.
Max.
—
Program and erase cycles (1, 3, 4)
VCC1 = 3.3 V, Topr = 25°C
10,000 (2)
times
—
Two words program time
VCC1 = 3.3 V, Topr = 25°C
300
4000
s
—
Lock bit program time
VCC1 = 3.3 V, Topr = 25°C
140
3000
s
—
Block erase time
VCC1 = 3.3 V, Topr = 25°C0.2
3.0
s
td(SR-SUS) Time delay from suspend request
until suspend
5 + CPU clock
× 3 cycles
ms
—
Interval from erase start/restart
until following suspend request
0
s
—
Suspend interval necessary for
auto-erasure to complete (7)
20
ms
—
Time from suspend until erase
restart
30 + CPU clock
× 1 cycle
s
—
Program, erase voltage
2.7
3.6
V
—
Read voltage
2.7
3.6
V
—
Program, erase temperature
-20/-40
85
°C
tPS
Flash Memory Circuit Stabilization Wait Time
50
s
—
Data hold time (6)
Ambient temperature = 55
°C
20
year
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