參數(shù)資料
型號： R5F36CAKNFA
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 81/92頁
文件大?。?/td> 769K
代理商： R5F36CAKNFA
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 82 of 90
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
5.3.4
Switching Characteristics (Memory Expansion Mode and Microprocessor
Mode (in No Wait State Setting))
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
Notes:
1.
Calculated according to the BCLK frequency as follows:
f
f(BCLK) is 12.5 MHz or less.
2.
Calculated according to the BCLK frequency as follows:
This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t=
CR × ln(1 V
OL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ,
hold time of output low level is
t =
30 pF × 1 k Ω × In(1 0.2V
CC2/VCC2)
= 6.7 ns.
Table 5.54
Memory Expansion and Microprocessor Modes (in No Wait State Setting)
Symbol
Parameter
Measuring
Condition
Standard
Unit
Min.
Max.
td(BCLK-AD)
Address output delay time
See
30
ns
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0ns
th(RD-AD)
Address output hold time (in relation to RD)
0ns
th(WR-AD)
Address output hold time (in relation to WR)
ns
td(BCLK-CS)
Chip select output delay time
30
ns
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
0ns
td(BCLK-ALE)
ALE signal output delay time
25
ns
th(BCLK-ALE)
ALE signal output hold time
4ns
td(BCLK-RD)
RD signal output delay time
30
ns
th(BCLK-RD)
RD signal output hold time
0ns
td(BCLK-WR)
WR signal output delay time
30
ns
th(BCLK-WR)
WR signal output hold time
0ns
td(BCLK-DB)
Data output delay time (in relation to BCLK)
40
ns
th(BCLK-DB)
Data output hold time (in relation to BCLK) (3)
0ns
td(DB-WR)
Data output delay time (in relation to WR)
ns
th(WR-DB)
Data output hold time (in relation to WR) (3)
ns
td(BCLK-HLDA)
HLDA output delay time
40
ns
0.5x10
9
f
BCLK
()
----------------------
40 ns
[]
–
0.5x10
9
f
BCLK
()
----------------------
10 ns
[]
–
DBi
R
C
相關PDF資料
PDF描述
R5F36CAKNFB 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100
R5F36CA6DFA 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100
R5F36CA6DFB 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100
R5F36CA6NFB 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100
R5F36S16DFB 16-BIT, FLASH, 32.72 MHz, MICROCONTROLLER, PQFP100
相關代理商/技術參數(shù)
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