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參數(shù)資料
| 型號(hào)： | R5F36CA6DFA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 73/99頁(yè) |
| 文件大小： | 759K |
| 代理商： | R5F36CA6DFA |
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R01DS0034EJ0200 Rev.2.00
Page 75 of 95
Feb 07, 2011
M16C/6C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Switching Characteristics
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.2.4.3
In 2 or 3 Waits Setting, and When Accessing External Area and Using
Multiplexed Bus
Notes:
1.
Calculated according to the BCLK frequency as follows:
2.
Calculated according to the BCLK frequency as follows:
n is 2 for 2-wait setting, 3 for 3-wait setting.
3.
Calculated according to the BCLK frequency as follows:
4.
Calculated according to the BCLK frequency as follows:
5.
When using multiplex bus, set f(BCLK) 12.5 MHz or less.
Table 5.39
Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When
Accessing External Area and Using Multiplexed Bus) (5)
Symbol
Parameter
Measuring
Condition
Standard
Unit
Min.
Max.
td(BCLK-AD)
Address output delay time
See
25
ns
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0ns
th(RD-AD)
Address output hold time (in relation to RD)
(Note 1)
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 1)
ns
td(BCLK-CS)
Chip select output delay time
25
ns
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
0ns
th(RD-CS)
Chip select output hold time (in relation to RD)
(Note 1)
ns
th(WR-CS)
Chip select output hold time (in relation to WR)
(Note 1)
ns
td(BCLK-RD)
RD signal output delay time
25
ns
th(BCLK-RD)
RD signal output hold time
0ns
td(BCLK-WR)
WR signal output delay time
25
ns
th(BCLK-WR)
WR signal output hold time
0ns
td(BCLK-DB)
Data output delay time (in relation to BCLK)
40
ns
th(BCLK-DB)
Data output hold time (in relation to BCLK)
0ns
td(DB-WR)
Data output delay time (in relation to WR)
(Note 2)
ns
th(WR-DB)
Data output hold time (in relation to WR)
(Note 1)
ns
td(BCLK-ALE)
ALE signal output delay time (in relation to BCLK)
15
ns
th(BCLK-ALE)
ALE signal output hold time (in relation to BCLK)
4ns
td(AD-ALE)
ALE signal output delay time (in relation to Address)
(Note 3)
ns
th(AD-ALE)
ALE signal output hold time (in relation to Address)
(Note 4)
ns
td(AD-RD)
RD signal output delay from the end of address
0ns
td(AD-WR)
WR signal output delay from the end of address
0ns
tdz(RD-AD)
Address output floating start time
8ns
0.5
10
9
×
f
BCLK
()
----------------------10 ns
[]
–
n
0.5
–
() 10
9
×
f
BCLK
()
------------------------------------40 ns
[]
–
0.5
10
9
×
f
BCLK
()
----------------------25 ns
[]
–
0.5
10
9
×
f
BCLK
()
----------------------15 ns
[]
–
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