
R01UH0197EJ0120 Rev.1.20
Jul 21, 2011
M16C/6B Group
13. Serial Interface
13.1.1
Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data.
Table 13.1 lists the
i = 0 to 2
NOTES:
1.
When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
2.
If an overrun error occurs, the receive data of the UiRB register will be indeterminate. The IR bit in the SiRIC
register does not change to 1 (interrupt requested).
3.
Bits U0IRS and U1IRS correspond to bits 0 and 1 in the UCON register respectively. U2IRS bit is in U2C1
register respectively.
Table 13.1
Clock Synchronous Serial I/O Mode Specifications
Item
Specification
Transfer data format
Transfer data length: 8 bits
Transfer clock
CKDIR bit in the UiMR register = 0 (internal clock): fj / (2 (n + 1))
fj = f1SIO, f2SIO, f8SIO, f32SIO
n = setting value of UiBRG register
00h to FFh
CKDIR bit = 1 (external clock): input from CLKi pin
Transmission,
reception control
Selectable from CTS function, RTS function or CTS/RTS function disable
Transmission start
condition
Before transmission starts, satisfy the following requirements
(1) The TE bit in the UiC1 register = 1 (transmission enabled)
The TI bit in the UiC1 register = 0 (data present in UiTB register)
If CTS function is selected, input on the CTSi pin = “L”
Reception start condition
Before reception starts, satisfy the following requirements
(1) The RE bit in the UiC1 register = 1 (reception enabled)
The TE bit in the UiC1 register = 1 (transmission enabled)
The TI bit in the UiC1 register = 0 (data present and dummy written in the UiTB register)
Interrupt request
generation timing
For transmission, one of the following conditions can be selected
The UiIRS bit
(3) = 0 (transmit buffer empty):
when transferring data from the UiTB register to the UARTi transmit register (at start of
transmission)
The UiIRS bit = 1 (transfer completed):
when the serial interface finished sending data from the UARTi transmit register
For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
This error occurs if the serial interface started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
Select function
CLK polarity selection
Transfer data input/output can be chosen to occur synchronously with the rising or the
falling edge of the transfer clock
LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be
selected
Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
Switching serial data logic
This function reverses the logic value of the transmit/receive data
Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
Separate CTS/RTS pins (UART0)
CTS0 and RTS0 are input/output from separate pins