參數(shù)資料
型號(hào)： R5F364AMDFA
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù)： 82/90頁(yè)
文件大?。?/td> 1261K
代理商： R5F364AMDFA
Page 83 of 88
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
Switching Characteristics
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
5.3.4.2
In 1 to 3 Waits Setting and When Accessing External Area
Notes:
1.
Calculated according to the BCLK frequency as follows:
2.
Calculated according to the BCLK frequency as follows:
3.
This standard value shows the timing when the output is
off, and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-
up (pull-down) resistance value.
Hold time of data bus is expressed in
t=
CR × ln(1V
OL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ,
hold time of output low level is
t =
30 pF × 1 kΩ × In(1 0.2V
CC2/VCC2)
= 6.7 ns.
Table 5.55
Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When
Accessing External Area)
Symbol
Parameter
Measuring
Condition
Standard
Unit
Min.
Max.
td(BCLK-AD)
Address output delay time
See
30
ns
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0ns
th(RD-AD)
Address output hold time (in relation to RD)
0ns
th(WR-AD)
Address output hold time (in relation to WR)
ns
td(BCLK-CS)
Chip select output delay time
30
ns
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
0ns
td(BCLK-ALE)
ALE signal output delay time
25
ns
th(BCLK-ALE)
ALE signal output hold time
-4
ns
td(BCLK-RD)
RD signal output delay time
30
ns
th(BCLK-RD)
RD signal output hold time
0ns
td(BCLK-WR)
WR signal output delay time
30
ns
th(BCLK-WR)
WR signal output hold time
0ns
td(BCLK-DB)
Data output delay time (in relation to BCLK)
40
ns
th(BCLK-DB)
Data output hold time (in relation to BCLK) (3)
0ns
td(DB-WR)
Data output delay time (in relation to WR)
ns
th(WR-DB)
Data output hold time (in relation to WR) (3)
ns
td(BCLK-HLDA)
HLDA output delay time
40
ns
n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
When n = 1, f(BCLK) is 12.5 MHz or less.
n
0.5
+
() 10
9
×
f
BCLK
()
------------------------------------
40 ns
[]
–
0.5
10
9
×
f
BCLK
()
----------------------10 ns
[]
–
DBi
R
C
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