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參數(shù)資料
| 型號： | R5F364AMDFA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 39/90頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | R5F364AMDFA |
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Page 44 of 88
5. Electrical Characteristics
5.1.5
Flash Memory Electrical Characteristics
Notes:
1.
Set the PM17 bit in the PM1 register to 1 (one wait).
2.
When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in
the PM1 register to 1 (one wait)
3.
Set the PM17 bit in the PM1 register to 1 (one wait). When using 125 kHz on-chip oscillator clock or sub clock as
the CPU clock source, a wait is not necessary.
Notes:
1.
Definition of program and erase cycles:
The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n
(n = 1,000), each block can be erased n times. For example, if a 64 Kbyte block is erased after writing two word
data 16,384 times, each to a different address, this counts as one program and erase cycles. Data cannot be
written to the same address more than once without erasing the block (rewrite prohibited).
2.
Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3.
In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase
operations to a certain number.
4.
If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5.
Customers desiring program/erase failure rate information should contact their Renesas technical support
representative.
6.
The data hold time includes time that the power supply is off or the clock is not supplied.
Table 5.8
CPU Clock When Operating Flash Memory (f(BCLK))
VCC1 = 2.7 to 5.5 V, Topr = -20 to 85°C/-40 to 85°C unless otherwise specified.
Symbol
Parameter
Conditions
Standard
Unit
Min.
Typ.
Max.
-
CPU rewrite mode
10 (1)
MHz
f(SLOW_R)
Slow read mode
5 (3)
MHz
-
Low current consumption read mode
fC(32.768)
35
kHz
-
Data flash read
2.7 V
≤ V
CC1 ≤ 3.0 V
16 (2)
MHz
3.0 V < VCC1 ≤ 5.5 V
20 (2)
MHz
Table 5.9
Flash Memory (Program ROM 1, 2) Electrical Characteristics
VCC1 = 2.7 to 5.5 V at Topr = 0 to 60°C (option: -40°C to 85°C), unless otherwise specified.
Symbol
Parameter
Conditions
Standard
Unit
Min.
Typ.
Max.
-
VCC1 = 3.3 V, Topr = 25°C
1,000 (2)
times
-
Two words program time
VCC1 = 3.3 V, Topr = 25°C
150
4000
μs
-
Lock bit program time
VCC1 = 3.3 V, Topr = 25°C
70
3000
μs
-
Block erase time
VCC1 = 3.3 V, Topr = 25°C
0.2
3.0
s
-
Program, erase voltage
2.7
5.5
V
-
Read voltage
2.7
5.5
V
-
Program, erase temperature
0
60
°C
tPS
Flash Memory Circuit Stabilization Wait Time
50
μs
-
Data hold time (6)
Ambient temperature = 55
°C
20
year
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