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參數(shù)資料
| 型號： | R5F363BEDFE |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 86/115頁 |
| 文件大?。?/td> | 2363K |
| 代理商： | R5F363BEDFE |
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REJ03B0271-0100 Rev.1.00 Sep 15, 2009
Page 72 of 113
M16C/63 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
5.2.4
Switching Characteristics (Memory Expansion Mode and Microprocessor
Mode)
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
5.2.4.1
In No Wait State Setting
Notes:
1.
Calculated according to the BCLK frequency as follows:
f(BCLK) is 12.5 MHz or less.
2.
Calculated according to the BCLK frequency as follows:
3.
This standard value shows the timing when the output is off, and does not
show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up (pull-down)
resistance value.
Hold time of data bus is expressed in
t =
CR × ln(1V
OL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output
low level is
t =
30 pF × 1 kΩ × In(1 0.2V
CC2/VCC2)
= 6.7 ns.
Table 5.35
Memory Expansion Mode and Microprocessor Mode (in No Wait State Setting)
Symbol
Parameter
Measuring
Condition
Standard
Unit
Min.
Max.
td(BCLK-AD)
Address output delay time
See
25
ns
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0ns
th(RD-AD)
Address output hold time (in relation to RD)
0ns
th(WR-AD)
Address output hold time (in relation to WR)
ns
td(BCLK-CS)
Chip select output delay time
25
ns
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
0ns
td(BCLK-ALE)
ALE signal output delay time
15
ns
th(BCLK-ALE)
ALE signal output hold time
4ns
td(BCLK-RD)
RD signal output delay time
25
ns
th(BCLK-RD)
RD signal output hold time
0ns
td(BCLK-WR)
WR signal output delay time
25
ns
th(BCLK-WR)
WR signal output hold time
0ns
td(BCLK-DB)
Data output delay time (in relation to BCLK)
40
ns
th(BCLK-DB)
Data output hold time (in relation to BCLK) (3)
0ns
td(DB-WR)
Data output delay time (in relation to WR)
ns
th(WR-DB)
Data output hold time (in relation to WR) (3)
ns
td(BCLK-HLDA)
HLDA output delay time
40
ns
0.5
10
9
×
f
BCLK
()
----------------------40 ns
[]
–
0.5
10
9
×
f
BCLK
()
----------------------10 ns
[]
–
DBi
R
C
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| R5F363BENFE | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
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| R5F36406CDFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:cameras, televisions, household appliances, office equipment |
| R5F36406CNFA | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:cameras, televisions, household appliances, office equipment |
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