參數(shù)資料
型號(hào)： R5F363BEDFE
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 6/115頁
文件大小： 2363K
代理商： R5F363BEDFE
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
Page 103 of 113
M16C/63 Group
5. Electrical Characteristics
Figure 5.33
Timing Diagram
Read timing
Write timing
BCLK
CSi
ALE
DBi
ADi
BHE
WR, WRL
WRH
BCLK
CSi
ALE
DBi
ADi
BHE
RD
tcyc
td(BCLK-CS)
30ns(max.)
Hi-Z
tsu(DB-RD)
50ns(min.)
Hi-Z
V
= V
= 3 V
CC1
CC2
Memory Expansion Mode and Microprocessor Mode
(in wait state setting 2
φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and
when inserting 1 to 3 recovery cycles and accessing external area)
n: 3 (when 2
φ + 3φ)
4 (when 2
φ + 4φ or 3φ + 4φ)
5 (when 4
φ + 5φ)
th(BCLK-CS)
0ns(min.)
td(BCLK-AD)
30ns(max.)
th(BCLK-AD)
0ns(min.)
td(BCLK-ALE)
25ns(max.)
th(BCLK-ALE)
-4ns(min.)
td(BCLK-RD)
30ns(max.)
th(BCLK-RD)
0ns(min.)
th(RD-DB)
0ns(min.)
tcyc
td(BCLK-CS)
30ns(max.)
td(BCLK-AD)
30ns(max.)
th(BCLK-ALE)
-4ns(min.)
td(BCLK-ALE)
25ns(max.)
td(BCLK-WR)
30ns(max.)
td(BCLK-DB)
40ns(max.)
th(BCLK-CS)
0ns(min.)
th(BCLK-AD)
0ns(min.)
th(WR-AD)
(m × t
-10)ns(min.)
cyc
th(BCLK-WR)
0ns(min.)
th(BCLK-DB)
0ns(min.)
th(WR-DB)
(m × t
-10)ns(min.)
cyc
(n × t
-60)ns(max.)
cyc
tac4(RD-DB)
(n × t
-40)ns(min.)
cyc
td(DB-WR)
tcyc =
1
m: 1 (when 1 recovery cycle inserted )
2 (when 2 recovery cycles inserted)
3 (when 3 recovery cycles inserted)
Measuring conditions
V
= V
= 3 V
CC1
CC2
Input timing voltage: V = 0.6 V, V
= 2.4 V
IL
IH
Output timing voltage: V
= 1.5 V, V
= 1.5 V
OL
OH
th(RD-AD)
(m × t
+0)ns(min.)
cyc
f(BCLK)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
R5F363BENFE 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU
R5F363BENFE#U0 制造商:Renesas Electronics Corporation 功能描述:M16C63 256+24/20KB -20 85C 80LQFP - Trays
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R5F36406CDFB 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:cameras, televisions, household appliances, office equipment
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