參數(shù)資料
型號(hào): R5F2L3AACDFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 18/74頁
文件大?。?/td> 959K
代理商: R5F2L3AACDFP
26
2588F–AVR–06/2013
ATtiny261/461/861
mencing normal operation. The watchdog oscillator is used for timing this real-time part of the
start-up time. The number of WD oscillator cycles used for each time-out is shown in Table 6-2.
6.2.1
External Clock
To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-
2. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Figure 6-2.
External Clock Drive Configuration
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
Note that the system clock prescaler can be used to implement run-time changes of the internal
clock frequency. See “System Clock Prescaler” on page 31 for details.
6.2.2
High-Frequency PLL Clock
The internal PLL generates a clock signal with a frequency eight times higher than the source
input. The PLL uses the output of the internal 8 MHz oscillator as source and the default setting
generates a fast peripheral clock signal of 64 MHz.
Table 6-2.
Number of Watchdog Oscillator Cycles
Typ Time-out
Number of Cycles
4 ms
512
64 ms
8K (8,192)
Table 6-3.
Start-up Times for the External Clock Selection
SUT1:0
Start-up Time from Power-
down and Power-save
Additional Delay from
Reset
Recommended Usage
00
6 CK
14CK
BOD enabled
01
6 CK
14CK + 4 ms
Fast rising power
10
6 CK
14CK + 64 ms
Slowly rising power
11
Reserved
EXTERNAL
CLOCK
SIGNAL
CLKI
GND
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