
R8C/3JM Group
R01UH0285EJ0100 Rev.1.00
Aug 08, 2011
20.10 Notes on Timer RD
20.10.1 TRDSTR Register
Set the TRDSTR register using the MOV instruction.
When the CSELi (i = 0 to 1) bit is set to 0 (the count stops at compare match of registers TRDi and
TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is
written to the TSTARTi bit.
Therefore, set the TSTARTi bit to 0 to change other bits without changing the TSTARTi bit when the CSELi
bit is se to 0.
To stop counting by a program, set the TSTARTi bit after setting the CSELi bit to 1. Although the CSELi bit
is set to 1 and the TSTARTi bit is set to 0 at the same time (with 1 instruction), the count cannot be stopped.
A, B, C, or D) pin with the timer RD output.
20.10.2 TRDi Register (i = 0 or 1)
When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register is
set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then
write.
If the timing for setting the TRDi register to 0000h overlaps with the timing for writing the value to the TRDi
register, the value is not written and the TRDi register is set to 0000h.
These precautions are applicable when selecting the following by bits CCLR2 to CCLR0 in the TRDCRi
register.
- 001b (Clear the TRDi register by input capture/compare match in the TRDGRAi register.)
- 010b (Clear the TRDi register by input capture/compare match in the TRDGRBi register.)
- 011b (Synchronous clear)
- 101b (Clear the TRDi register by input capture/compare match in the TRDGRCi register.)
- 110b (Clear the TRDi register by input capture/compare match in the TRDGRDi register.)
When writing the value to the TRDi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Program example
MOV.W
#XXXXh, TRD0
;Writing
JMP.B
L1
;JMP.B
L1:
MOV.W
TRD0,DATA
;Reading
20.10.3 TRDSRi Register (i = 0 or 1)
When writing the value to the TRDSRi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Program example
MOV.B
#XXh, TRDSR0
;Writing
JMP.B
L1
;JMP.B
L1:
MOV.B
TRDSR0,DATA
;Reading
20.10.4 TRDCRi Register (i = 0 or 1)
To set bits TCK2 to TCK0 in the TRDCRi register to 111b (fOCO-F), set fOCO-F to the clock frequency higher
than the CPU clock frequency.
Table 20.18
TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops
Count Stop
TRDIOji Pin Output when Count Stops
When the CSELi bit is set to 1, set the
TSTARTi bit to 0 and the count stops.
The pin holds the output level immediately before the count stops. (The pin
outputs the initial output level selected by bits OLS0 and OLS1 in the
TRDFCR register in complementary and reset synchronous PWM modes.)
When the CSELi bit is set to 0, the
count stops at compare match of
registers TRDi and TRDGRAi.
The pin holds the output level after the output changes by compare match.
(The pin outputs the initial output level selected by bits OLS0 and OLS1 in the
TRDFCR register in complementary and reset synchronous PWM modes.)