參數(shù)資料
型號: R5F213G6ADNP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQCC24
封裝: 4 X 4 MM, 0.50 MM PITCH, PLASTIC, QFN-24
文件頁數(shù): 4/56頁
文件大?。?/td> 431K
代理商: R5F213G6ADNP
R8C/3GA Group
2. Central Processing Unit (CPU)
REJ03B0235-0110 Rev.1.10 Sep. 10, 2009
Page 12 of 53
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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