參數(shù)資料
型號: R5F213G6ADNP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQCC24
封裝: 4 X 4 MM, 0.50 MM PITCH, PLASTIC, QFN-24
文件頁數(shù): 28/56頁
文件大?。?/td> 431K
代理商: R5F213G6ADNP
R8C/3GA Group
5. Electrical Characteristics
REJ03B0235-0110 Rev.1.10 Sep. 10, 2009
Page 34 of 53
Notes:
1.
The measurement condition is VCC = 1.8 V to 5.5 V and Topr =
20 to 85°C (N version) / 40 to 85°C (D version).
2.
The voltage detection level varies with detection targets. Select the level with the VCA24 bit in the VCA2 register.
3.
Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
4.
Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Notes:
1.
The measurement condition is Topr =
20 to 85°C (N version) / 40 to 85°C (D version), unless otherwise specified.
2.
To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
Table 5.11
Voltage Detection 2 Circuit Electrical Characteristics
Symbol
Parameter
Condition
Standard
Unit
Min.
Typ.
Max.
Vdet2
Voltage detection level Vdet2_0 (2)
At the falling of VCC
3.70
4.00
4.30
V
Voltage detection level Vdet2_EXT (2)
At the falling of LVCMP2
1.20
1.34
1.48
V
Hysteresis width at the rising of VCC in voltage detection
2 circuit
0.10
V
Voltage detection 2 circuit response time (3)
At the falling of VCC from
5 V to (Vdet2_0
0.1) V
20
150
s
Voltage detection circuit self power consumption
VCA27 = 1, VCC = 5.0 V
1.7
A
td(E-A)
Waiting time until voltage detection circuit operation
starts (4)
100
s
Table 5.12
Power-on Reset Circuit (2)
Symbol
Parameter
Condition
Standard
Unit
Min.
Typ.
Max.
trth
External power VCC rise gradient
0
50000
mV/msec
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit of Hardware Manual (REJ09B0472) for details.
2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain
tw(por) for 1 ms or more.
Vdet0 (1)
0.5 V
Internal
reset signal
tw(por) (2)
Voltage detection 0
circuit response time
Vdet0 (1)
1
fOCO-S
× 32
1
fOCO-S
× 32
External
Power VCC
trth
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