參數(shù)資料
型號(hào)： R5F21388WJFP
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP80
封裝： 12 X 12MM, 0.5MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 44/70頁
文件大?。?/td> 632K
代理商： R5F21388WJFP
R8C/38W Group, R8C/38X Group, R8C/38Y Group, R8C/38Z Group
5. Electrical Characteristics
Under development Preliminary document
Specifications in this document are tentative and subject to change.
REJ03B0317-0010 Rev.0.10
Page 49 of 67
May 31, 2010
Notes:
1.
VCC = 2.7 to 5.5 V at Topr =
40 to 85°C (J version) / 40 to 125°C (K version), unless otherwise specified.
2.
Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100, 1,000, 10,000), each block can be erased n times. For example, if
1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3.
Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4.
In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
5.
If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6.
Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7.
The data hold time includes time that the power supply is off or the clock is not supplied.
8.
This data hold time includes 3,000 hours in Ta = 125
°C and 7,000 hours in Ta = 85°C.
Figure 5.2
Time delay until Suspend
Table 5.6
Flash Memory (Data flash Block A to Block D) Electrical Characteristics
Symbol
Parameter
Conditions
Standard
Unit
Min.
Typ.
Max.
Program/erase endurance (2)
10,000 (3)
times
Byte program time
(program/erase endurance
≤ 1,000 times)
160
950
s
Byte program time
(program/erase endurance
> 1,000 times)
300
950
s
Block erase time
(program/erase endurance
≤ 1,000 times)
0.2
1
s
Block erase time
(program/erase endurance
> 1,000 times)
0.3
1
s
td(SR-SUS)
Time delay from suspend request until
suspend
3+CPU clock ×
3 cycles
ms
Interval from erase start/restart until
following suspend request
0
s
Time from suspend until erase restart
30+CPU clock ×
1 cycle
s
td(CMDRST-
READY)
Time from when command is forcibly
terminated until reading is enabled
30+CPU clock ×
1 cycle
s
Program, erase voltage
2.7
5.5
V
Read voltage
2.7
5.5
V
Program, erase temperature
40
85 (J version)
125 (K version)
°C
Data hold time (7)
Ambient temperature = 55
°C (8)
20
year
FST6 bit
Suspend request
(FMR21 bit)
Fixed time
td(SR-SUS)
Clock-dependent
time
Access restart
FST6, FST7: Bit in FST register
FMR21: Bit in FMR2 register
FST7 bit
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相關(guān)代理商/技術(shù)參數(shù)
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