
R8C/2C Group, R8C/2D Group
6. Voltage Detection Circuit
Rev.2.00
Dec 05, 2007
REJ09B0339-0200
Figure 6.7
VW1C Register
Voltage Monitor 1 Circuit Control Register (1)
Symbol
Address
After Reset(8)
VW1C
0036h
00001000b
Bit Symbol
Bit Name
Function
RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
b2
0 : Not detected
1 : Vdet1 crossing detected
RW
b1 b0
b3
b7 b6 b5 b4
VW1C0
RW
Voltage monitor 1 interrupt/reset
enable bit(6)
0 : Disable
1 : Enable
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
RW
VW1C2
Voltage change detection
flag(3, 4, 8)
VW1C1
Voltage monitor 1 digital filter
disable mode select bit(2)
VW1C3
Voltage detection 1 signal monitor
flag(3, 8)
VW1F1
RW
Sampling clock select bits
b5 b4
0 0 : fOCO-S divided by 1
0 1 : fOCO-S divided by 2
1 0 : fOCO-S divided by 4
1 1 : fOCO-S divided by 8
VW1F0
RW
0 : VCC < Vdet1
1 : VCC ≥ Vdet1 or voltage detection 1
circuit disabled
RO
VW1C6
Voltage monitor 1 circuit mode
select bit(5)
0 : Voltage monitor 1 interrupt mode
1 : Voltage monitor 1 reset mode
RW
VW1C7
Voltage monitor 1 interrupt/reset
generation condition select bit(7, 9)
0 : When VCC reaches Vdet1 or above
1 : When VCC reaches Vdet1 or below
RW
When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or
below ). (Do not set to 0.)
Set the PRC3 bit in the PRCR register to 1 (rew rite enable) before w riting to the VW1C register.
To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting
1.
Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit
enabled).
Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 interrupt/enabled reset).
The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).
Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).
The VW1C7 bit is enabled w hen the VW1C1 bit is set to 1 (digital filter disabled mode).
Bits VW1C2 and VW1C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset,
or voltage monitor 2 reset.