參數(shù)資料
型號(hào): R5F212BASDFA
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP48
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 50/138頁
文件大?。?/td> 492K
代理商: R5F212BASDFA
230
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
Bit 3– AC1ICE: Analog Comparator 1 Interrupt Capture Enable bit
Set this bit to enable the input capture of the Timer/Counter1 on the analog comparator event.
The comparator output is in this case directly connected to the input capture front-end logic,
making the comparator utilize the noise canceler and edge select features of the
Timer/Counter1 Input Capture interrupt. To make the comparator trigger the Timer/Counter1
Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set.
rising edge of AC1O is the capture/trigger event of the Timer/Counter1, in case ICES1 is set to
zero, it is the falling edge which is taken into account.
Clear this bit to disable this function. In this case, no connection between the Analog Compara-
tor and the input capture function exists.
Bit 2, 1, 0– AC1M2, AC1M1, AC1M0: Analog Comparator 1 Multiplexer register
These 3 bits determine the input of the negative input of the analog comparator.
The different setting are shown in Table 20-4.
20.2.3
Analog Comparator 2 Control Register – AC2CON
Bit 7– AC2EN: Analog Comparator 2 Enable Bit
Set this bit to enable the analog comparator 2.
Clear this bit to disable the analog comparator 2.
Table 20-3.
Interrupt sensitivity selection
AC1IS1
AC1IS0
Description
0
Comparator Interrupt on output toggle
01
Reserved
1
0
Comparator interrupt on output falling edge
1
Comparator interrupt on output rising edge
Table 20-4.
Analog Comparator 1 negative input selection
AC1M2
AC1M1
AC1M0
Description
000“Vref”/6.40
001“Vref”/3.20
010“Vref”/2.13
011“Vref”/1.60
100Analog Comparator Negative Input (ACMPM pin)
101DAC result
110Reserved
111Reserved
Bit
7
654
3
2
1
0
AC2EN
AC2IE
AC2IS1
AC2IS0
AC2M2
AC2M1
AC2M0
AC2CON
Read/Write
R/W
-
R/W
Initial Value
0
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