參數(shù)資料
型號(hào)： R5F21264SDFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP32
封裝： 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁(yè)數(shù)： 23/52頁(yè)
文件大?。?/td> 620K
代理商： R5F21264SDFP
47
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
11.4
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is the typical value at
V
CC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer pres-
caler, the Watchdog Reset interval can be adjusted as shown in Table 11-2 on page 50. The WDR – Watchdog
Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a
Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the Atmel
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P resets and executes from the Reset
Vector. For timing details on the Watchdog Reset, refer to Table 11-2 on page 50.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety
levels are selected by the fuse WDTON as shown in Table 11-1. Refer to ”Timed Sequences for Changing the
Figure 11-7. Watchdog Timer.
11.4.1
Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are
described for each level.
11.4.1.1
Safety Level 1
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any
restriction. A timed sequence is needed when changing the Watchdog Time-out period or disabling an enabled
Watchdog Timer. To disable an enabled Watchdog Timer, and/or changing the Watchdog Time-out, the following
procedure must be followed:
1.
In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless
of the previous value of the WDE bit.
2.
Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with
the WDCE bit cleared.
Table 11-1.
WDT Configuration as a Function of the Fuse Settings of WDTON
WDTON
Safety level
WDT initial state
How to disable the WDT
How to change time-out
Unprogrammed
1
Disabled
Timed sequence
Programmed
2
Enabled
Always enabled
Timed sequence
WATCHDOG
OSCILLATOR
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