參數(shù)資料
型號: R5F21264SDFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù): 13/52頁
文件大?。?/td> 620K
代理商: R5F21264SDFP
38
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60 s to ensure that
the BOD is working correctly before the MCU continues executing code. BOD disable is controlled by bit 6, BODS
(BOD Sleep) in the control register MCUCR, see ”MCUCR – MCU Control Register” on page 56. Writing this bit to
one turns off the BOD in relevant sleep modes, while a zero in this bit keeps BOD active. Default setting keeps
BOD active, that is, BODS set to zero.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see ”MCUCR – MCU Control Regis-
Note:
1. BOD disable only available in the Atmel ATmega165PA/325PA/3250PA/645P/6450P picoPower devices.
10.4
Idle mode
When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU
but allowing the SPI, USART, Analog Comparator, ADC, USI, Timer/Counters, Watchdog, and the interrupt system
to continue operating. This sleep mode basically halts clk
CPU and clkFLASH, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer
Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not
required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control
and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conver-
sion starts automatically when this mode is entered.
10.5
ADC Noise Reduction mode
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode,
stopping the CPU but allowing the ADC, the external interrupts, the USI start condition detection, Timer/Counter2,
and the Watchdog to continue operating (if enabled). This sleep mode basically halts clk
I/O, clkCPU, and clkFLASH,
while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is
enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete
interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, a
Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change
interrupt can wake up the MCU from ADC Noise Reduction mode.
10.6
Power-down mode
When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this
mode, the external Oscillator is stopped, while the external interrupts, the USI start condition detection, and the
Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI
start condition interrupt, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This
sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held
for some time to wake up the MCU. Refer to ”External interrupts” on page 57 for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up
becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up
period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in ”Clock
10.7
Power-save mode
When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This
mode is identical to Power-down, with one exception:
If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either Timer Overflow
or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in
TIMSK2, and the Global Interrupt Enable bit in SREG is set.
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