參數(shù)資料
型號(hào)： R5F21264JFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP32
封裝： 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁(yè)數(shù)： 9/52頁(yè)
文件大小： 620K
代理商： R5F21264JFP
34
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
9.8
Timer/Counter oscillator
Atmel ATmega169P uses the same XTAL oscillator for Low-frequency Oscillator and Timer/Counter Oscillator.
See ”Low-frequency XTAL Oscillator” on page 31 for details on the oscillator and XTAL requirements.
ATmega169P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. When using
the Timer/Counter Oscillator, the system clock needs to be four times the oscillator frequency. Due to this and the
pin sharing, the Timer/Counter Oscillator can only be used when the Calibrated Internal RC Oscillator is selected
as system clock source.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is written to logic one.
See ”Asynchronous operation of the Timer/Counter” on page 135 for further description on selecting external clock
as input instead of a 32.768kHz watch XTAL.
9.9
Clock output buffer
When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is suitable when chip
clock is used to drive other circuits on the system. The clock will be output also during reset and the normal opera-
tion of I/O pin will be overridden when the fuse is programmed. Any clock source, including internal RC Oscillator,
can be selected when CLKO serves as clock output. If the System Clock Prescaler is used, it is the divided system
clock that is output when the CKOUT Fuse is programmed.
9.10
System clock prescaler
The Atmel ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P system clock can be
divided by setting the ”CLKPR – Clock Prescale Register” on page 35. This feature can be used to decrease the
system clock frequency and power consumption when the requirement for processing power is low. This can be
used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripher-
als. clk
I/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 9-14 on page 36.
9.10.1
Switching time
When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock
system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous
setting, nor the clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster
than the CPU’s clock frequency. Hence, it is not possible to determine the state of the prescaler – even if it were
readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock fre-
quency is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and
T2 is the period corresponding to the new prescaler setting.
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