參數(shù)資料
型號(hào)： R5F101FAAFP#V0
廠商： Renesas Electronics America
文件頁(yè)數(shù)： 191/395頁(yè)
文件大?。?/td> 0K
描述： MCU 16BIT 16KB FLASH 44LQFP
產(chǎn)品培訓(xùn)模塊： RL78 ADC
標(biāo)準(zhǔn)包裝： 1
系列： RL78/G13
核心處理器： RL78
芯體尺寸： 16-位
速度： 32MHz
連通性： CSI，I²C，LIN，UART/USART
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 31
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x8/10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LQFP
包裝： 托盤(pán)
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2005 Microchip Technology Inc.
DS39612B-page 269
PIC18F6525/6621/8525/8621
24.3
Power-Down Mode (Sleep)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (RCON<3>) is cleared, the
TO (RCON<4>) bit is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or high-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are high-impedance inputs, high or low externally,
to avoid switching currents caused by floating inputs.
The T0CKI input should also be at VDD or VSS for low-
est current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
24.3.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1.
External Reset input on MCLR pin.
2.
Watchdog
Timer
wake-up
(if
WDT
was
enabled).
3.
Interrupt from INTx pin, RB port change or a
peripheral interrupt.
The following peripheral interrupts can wake the device
from Sleep:
1.
PSP read or write.
2.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
3.
TMR3 interrupt. Timer3 must be operating as an
asynchronous counter.
4.
CCP Capture mode interrupt (Capture will not
occur).
5.
MSSP (Start/Stop) bit detect interrupt.
6.
MSSP transmit or receive in Slave mode
(SPI/I2C).
7.
USART RXx or TXx (Synchronous Slave mode).
8.
A/D conversion (when A/D clock source is RC).
9.
EEPROM write operation complete.
10. LVD interrupt.
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
External MCLR Reset will cause a device Reset. All
other events are considered a continuation of program
execution and will cause a “wake-up”. The TO and PD
bits in the RCON register can be used to determine the
cause of the device Reset. The PD bit, which is set on
power-up, is cleared when Sleep is invoked. The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 2) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the
interrupt address. In cases where the execution of the
instruction following Sleep is not desirable, the user
should have a NOP after the SLEEP instruction.
24.3.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
If an interrupt condition (interrupt flag bit and
interrupt enable bits are set) occurs before the
execution of a SLEEP instruction, the SLEEP
instruction will complete as a NOP. Therefore, the
WDT and WDT postscaler will not be cleared, the
TO bit will not be set and PD bits will not be
cleared.
If the interrupt condition occurs during or after
the execution of a SLEEP instruction, the device
will immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP
instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT
instruction should be executed before a SLEEP
instruction.
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