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參數(shù)資料
| 型號： | R1LP0408C-I |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | R1LP0408C-I Series Datasheet 78K/AUG.01.03 |
| 中文描述： | R1LP0408C - I系列數(shù)據(jù)78K/AUG.01.03 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 78K |
| 代理商： | R1LP0408C-I |
R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 8 of 13
Write Cycle
R1LP0408C-I
-5
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
OHZ
55
20
20
70
25
25
ns
Chip selection to end of write
50
60
ns
4
Address setup time
0
0
ns
5
Address valid to end of write
50
60
ns
Write pulse width
40
50
ns
3, 12
Write recovery time
0
0
ns
6
Write to output in high-Z
0
0
ns
1, 2, 7
Data to write time overlap
25
30
ns
Data hold from write time
0
0
ns
Output active from end of write
5
5
ns
2
Output disable to output in high-Z
Notes: 1. t
, t
and t
are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (t
) of a low CS# and a low WE#. A write begins at the later
transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going
high or WE# going high. t
WP
is measured from the beginning of write to the end of write.
4. t
CW
is measured from CS# going low to the end of write.
5. t
AS
is measured from the address valid to the beginning of write.
6. t
WR
is measured from the earlier of WE# or CS# going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase
to the outputs must not be applied.
8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of
the opposite phase to the outputs must not be applied to them.
12. In the write cycle with OE# low fixed, t
WP
must satisfy the following equation to avoid a problem
of data bus contention. t
WP
≥
t
DW
min + t
WHZ
max
0
0
ns
1, 2, 7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R1LP0408CSB#5SC | 制造商:Renesas Electronics Corporation 功能描述: |
| R1LP0408CSB-5SC | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4M SRAM (512-kword 】 8-bit) |
| R1LP0408CSB-5SC#B0 | 制造商:Renesas Electronics Corporation 功能描述:SRAM ASYNC SGL 5V 4MBIT 512KX8 55NS 32TSOP-II - Trays 制造商:Renesas Electronics 功能描述:512k~8 55ns 4.5V to 5.5V TSOP 制造商:Renesas Electronics 功能描述:512k~8 55ns 4.5V to 5.5V TSOP Cut Tape 制造商:Renesas Electronics Corporation 功能描述:SRAM,Low Power,4Mb, x8, 55ns |
| R1LP0408CSB-5SC#BO | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM 4M 1LP0408 SOP32 |
| R1LP0408CSB-5SC#D0 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Async Single 5V 4M-Bit 512K x 8 55ns 32-Pin TSOP-II 制造商:Renesas Electronics Corporation 功能描述:SRAM ASYNC SGL 5V 4MBIT 512KX8 55NS 32TSOP-II - Trays 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:SRAM Chip Async Single 5V 4M-Bit 512K x 8 55ns 32-Pin TSOP-II |
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