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參數(shù)資料
| 型號： | QPI-8L |
| 廠商： | Vicor Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | AdvencedTCA Hot-Swap Sip With Active EMI Filter |
| 中文描述： | AdvencedTCA熱插拔有源EMI濾波器的SiP |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 268K |
| 代理商： | QPI-8L |
Picor Corporation www.picorpower.com
QPI-8L Data Sheet Rev. 1.0 Page 2 of 8
P
P
R
R
E
E
L
L
I
I
M
M
I
I
N
N
A
A
R
R
Y
Y
Absolute Maximum Ratings
–
Exceeding these parameters may result in permanent damage to the product.
Pins
Parameter
Notes
BUS+, SW, PWRGD to BUS- Input voltage
Continuous
BUS+, SW, PWRGD to BUS- Input voltage
100 ms transient
BUS+/BUS- to Shield
BUS inputs to shield hi-pot
QPI+ to QPI-
Load current
Pulsed limit @ 25°C
Package
Power dissipation
@ 25°C
Package
Operating temperature
PCB to QPI Interface
Package
Thermal resistance
θ
ja
Free Air
Package
Junction temperature
Tb = 100°C; Pd = 4 W @15 °C/W
Package
Thermal resistance
PCB layout dependent
(Note 1)
Package
Storage temperature
Package
Re-flow temperature
20 s exposure
All pins
ESD
HBM
Electrical Characteristics
–
Parameter limits apply over the operating temp. range unless otherwise noted.
Min
-0.5
Typ
Max
80
100
+/-1500
Units
Vdc
Vdc
Vdc
Adc
W
°C
°C/W
°C
°C/W
°C
°C
kV
12
4.0
100
50
160
15
125
212
+/-2
-40
-40
Symbol
V
b+b-
V
+oi
V
-oi
CMA
DMA
I BUS+ to BUS-
IPG QPI+ to QPI- Load current prior to PWRGD
UV
Undervoltage threshold rising
UVHYS
Undervoltage hysteresis falling
OV
Overvoltage threshold rising
OVHYS
Overvoltage hysteresis falling
PWGSAT
Powergood low voltage
PWGLK
Powergood high leakage
Parameter
BUS+ to BUS- input range
BUS+ to QPI+ voltage drop
BUS- to QPI- voltage drop
Common-mode attenuation
Differential-mode attenuation
Input bias current at 80 Volts
Notes
Measured at I
Load
= 5 A
(Note 2)
Measured at I
Load
= 5 A @ 100°C
(Note 2)
Measured at I
Load
= 5 A @ 100°C
(Note 2)
VBUS = 48 V; Frequency = 250 kHz
VBUS = 48 V; Frequency = 250 kHz
Input current from BUS+ to BUS-
Critical maximum DC load
Controller disabled to enabled
Controller enabled to disabled
Controller enabled to disabled
Controller disabled to enabled
IPWG = 1 mA
VPWG = 90 V
Min
UV
Typ
Max
80
Units
Vdc
mVdc
mVdc
dB
dB
mA
mA
V
V
V
V
V
μA
100
250
45
75
15
25
34
UV – 2 V
76
OV – 4 V
0.2
1
0.6
Note 1:
Refer to Figure 15 and QPI application note QPI-AN1 for critical PCB layout guidelines to achieve this thermal resistance when
reflowed onto the PCB.
QPI 8
SIP Package
(Bottom View)
9
10
11
12
4
3
2
1
8
7
6
5
13
14
15
16
NC
PWRGD
OV
BUS+
SHIELD SW
BUS-
QPI+
QPI-
BUS+
UVEN
SW
BUS-
Pin Descriptions
SiP Package Outline
(bottom view)
Pin
Name
Description
1, 16
BUS-
Negative bus potential
2, 3, 15
SW
Negative rail controlled by hot
insertion function.
4
SHIELD
Shield connects to the converter
shield and Y-capacitor common
point via RY. See
Figures 9a and 9b.
5, 6
QPI-
Negative input to the converter
7, 8
QPI+
Positive input to the converter
10
PWRGD
Open collector output that asserts
low when power is NOT good.
12, 13
BUS+
Positive bus potential
14
UVEN
High side of UV resistor divider
11
OV
High side of OV resistor divider
9
Not used
No connection
Note 2:
Refer to Figure 5 for current derating curve.
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