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參數(shù)資料
| 型號： | QLX4300SIQT7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC EQUALIZER REC 3.125GBPS 46QFN |
| 標準包裝： | 1 |
| 系列： | QLx™ |
| 應用： | 數(shù)據(jù)傳輸 |
| 電源電壓： | 1.1 V ~ 1.3 V |
| 封裝/外殼： | 46-WFQFN 裸露焊盤 |
| 供應商設(shè)備封裝： | 46-TQFN |
| 包裝： | 標準包裝 |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | QLX4300SIQT7-DKR QLX4300SIQT7-DKR-ND QLX4300SIQT7DKR |
17
FN6982.1
November 19, 2009
Detection Thereshold (DT) Pin Functionality
The QLx4300-S45 is capable of maintaining periods of
line silence on any of its four channels by monitoring
each channel for loss of signal (LOS) conditions and
subsequently muting the outputs of a respective channel
when such a condition is detected. A reference current
applied to the detection threshold (DT) pin is used to set
the LOS threshold of the internal signal detection
circuitry. Current control on the DT pin is done via one or
two external resistors. Nominally, both a pull-up and
pull-down resistor are tied to the DT pin (Figure 27A),
but if adequate control of the supply voltage is
maintained to within ±3% of 1.2V, then a simple pull
down resistor is adequate (as in Figure 27B). Resistors
used should be at least 1/16W, with ±1% precision.
The internal bias point of the DT pin, nominally 1.05V, is
used in conjunction with the voltage divider (R1 and R2)
shown in Figure 27A to set the reference current on the
DT pin.
Case 1: Channels with less than or equal to 17dB loss at
1.5625GHz:
For signals transmitted on channels having less than
or equal to 25dB of loss at 2.5GHz, the optimal DT
reference current is 0A. This optimal reference
current may be achieved by either leaving the DT pin
floating, or tying the DT pin to ground (GND) with a
10MΩ resistor.
Case 2: Channels with greater 17dB loss at 1.5625GHz:
For channels exhibiting more than 25dB of total loss
(this includes cable or FR-4 loss) the DT pin should
be configured for a reference sink current (coming
out of the DT pin) of approximately 2A. A typical
configuration for a 2A sink current is given in
utilized, a 525kΩ resistor is used.
R21
R20
R1
tSDI tHDI
tSCK
tHEN
DI
CLK
ENB
R1
R21
QLx4300-S45 (D)
QLx4300-S45 (C)
QLx4300-S45 (B)
QLx4300-S45 (A)
FIGURE 26. TIMING DIAGRAM FOR PROGRAMMING MULTIPLE QLx4300-S45 DEVICES USING DI/DO CARRYOVER
FIGURE 27A.
FIGURE 27B.
FIGURE 27C.
FIGURE 27.
QLx4300-S45
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