FN6982.1 November 19, 2009 Typical Application Reference Designs Figures 28 and 29 show reference design schematics for a QLx4300-S45 evaluatio" />
參數(shù)資料
型號: QLX4300SIQT7
廠商: Intersil
文件頁數(shù): 10/21頁
文件大?。?/td> 0K
描述: IC EQUALIZER REC 3.125GBPS 46QFN
標(biāo)準(zhǔn)包裝: 1
系列: QLx™
應(yīng)用: 數(shù)據(jù)傳輸
電源電壓: 1.1 V ~ 1.3 V
封裝/外殼: 46-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 46-TQFN
包裝: 標(biāo)準(zhǔn)包裝
安裝類型: 表面貼裝
其它名稱: QLX4300SIQT7-DKR
QLX4300SIQT7-DKR-ND
QLX4300SIQT7DKR
18
FN6982.1
November 19, 2009
Typical Application Reference Designs
Figures 28 and 29 show reference design schematics for a QLx4300-S45 evaluation board with an SMA connector
interface. Figure 28 shows the schematic for the case when the equalizer boost level is set via the CP pins. Figure 29
shows the schematic for the case when the level is set via the serial bus interface.
FIGURE 28. APPLICATION CIRCUIT FOR THE QLx4300-S45 EVALUATION BOARD USING THE CONTROL PINS FOR
SETTING THE EQUALIZER COMPENSATION LEVEL
1
2
3
4
5
6
7
8
46
45
44
43
42
41
40
39
16
17
18
19
20
21
22
23
9
10
11
12
13
14
15
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
DI
DO
CP
3
[A]
CP
3[B]
C
P3
[C
]
C
P4
[A
]
C
P4
[B
]
CP
4
[C
]
CL
K
E
NB
CP
1[A]
C
P1
[B
]
CP
1[
C]
CP
2[
A]
CP
2[B]
C
P2
[C
]
GND
IS2
IS1
MODE
IS4
IS3
1.2V
DT
IN1[P]
IN1[N]
IN2[P]
IN2[N]
IN3[P]
IN3[N]
IN4[P]
IN4[N]
OUT2[P]
OUT2[N]
OUT4[P]
OUT4[N]
OUT1[P]
OUT1[N]
OUT3[P]
OUT3[N]
6kO
BGREF
A
QLx4300-S45
1.2V
10
0
pF
*
10
n
F
Bypass circuit for each VDD pin: 4, 7, 10, 29, 32, 35
(*100pF capacitor should be positioned closest to the pin)
EQ Boost Control
for Channels 1 and 2
(See pages 15-17)
NC
Detection threshold
reference current
QLx4300-S45
LANE EXTENDER
Reference
Control Pin Mode
Quellan, Inc.
EQ Boost Control
for Channels 3 and 4
(See pages 15-17)
= SMA Connector
A) DC Blocking Capacitors = X7R or COG
0.1F (>4GHz bandwidth)
Impedance Select (Channels 3 and 4)
Impedance Select (Channels 1 and 2)
MODE
MODE at 1.2V: Serial Control Mode
MODE at GND: Binary Control Mode
1.2V
100k
47n
F
42
.2
k
Ω
QLx4300-S45
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