參數(shù)資料
型號： QL8150-8PUN196C
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 640 CLBS, 188946 GATES, PBGA196
封裝： 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, TFBGA-196
文件頁數(shù)： 78/96頁
文件大?。?/td> 1607K
代理商： QL8150-8PUN196C
2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
8
F
in represents a very stable high-frequency input clock and produces an accurate signal reference. This signal
can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass through the PLL itself.
Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external F
in signal and the
local VCO form a control loop. The VCO is multiplied or divided down to the reference frequency, so that a
phase detector (the crossed circle in Figure 6) can compare the two signals. If the phases of the external and
local signals are not within the tolerance required, the phase detector sends a signal through the charge pump
and loop filter (Figure 6). The charge pump generates an error voltage to bring the VCO back into alignment,
and the loop filter removes any high frequency noise before the error voltage enters the VCO. This new VCO
signal enters the clock tree to drive the chip's circuitry.
F
out represents the clock signal emerging from the output pad (the output signal PLLPAD_OUT is explained
in Table 7). The PLL always drives the PLLPAD_OUT signal, regardless of whether the PLL is configured for
on-chip use. The PLLPAD_OUT will not oscillate if PLL_RESET is asserted, or if the PLL is powered down.
The QL8325 and QL8250 devices contain four PLLs, the remaining Eclipse II devices do not contain PLLs.
There is one PLL located in each quadrant of the FPGA. QuickLogic PLLs compensate for the additional delay
created by the clock tree itself, as previously noted, by subtracting the clock tree delay through the feedback
path.
PLL Modes of Operation
QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output frequency—
Table 6 indicates the features of each mode.
NOTE: “HF” stands for “high frequency” and “LF” stands for “l(fā)ow frequency.”
The input frequency can range from 12.5 MHz to 440 MHz, while output frequency ranges from 25 MHz to
220 MHz. When adding PLLs to the top-level design, be sure that the PLL mode matches the desired input
and output frequencies.
Table 6: PLL Mode Frequencies
PLL Model
Output Frequency
Input Frequency Range
Output Frequency Range
PLL_HF
Same as input
66 MHz–220 MHz
PLL_LF
Same as input
25 MHz–66 MHz
PLL_MULT2HF
2x
33 MHz–110 MHz
66 MHz–220 MHz
PLL_MULT2LF
2x
12.5 MHz–33 MHz
25 MHz–66 MHz
PLL_DIV2HF
1/2x
220 MHz–440 MHz
110 MHz–220 MHz
PLL_DIV2LF
1/2x
50 MHz–220 MHz
25 MHz–110 MHz
PLL_MULT4
4x
12.5 MHz–50 MHz
50 MHz–200 MHz
PLL_DIV4
1/4x
100 MHz–440 MHz
25 MHz–110 MHz
相關PDF資料
PDF描述
QL8150-8PUN196I FPGA, 640 CLBS, 188946 GATES, PBGA196
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