參數(shù)資料
型號(hào)： QL8150-8PUN196C
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 640 CLBS, 188946 GATES, PBGA196
封裝： 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, TFBGA-196
文件頁(yè)數(shù)： 11/96頁(yè)
文件大?。?/td> 1607K
代理商： QL8150-8PUN196C
2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
19
Sample/Preload Instruction. The Sample/Preload Instruction allows a device to remain in its functional
mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this
test, the boundary scan register can be accessed through a data scan operation, allowing users to sample
the functional data entering and leaving the device.
Bypass Instruction. The Bypass Instruction allows data to skip a device boundary scan entirely, so the
data passes through the bypass register. The Bypass instruction allows users to test a device without passing
through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial
data to be transferred through a device without affecting the operation of the device.
JTAG BSDL Support
BSDL-Boundary Scan Description Language
Machine-readable data for test equipment to generate testing vectors and software
BSDL files available for all device/package combinations from QuickLogic
Extensive industry support available and ATVG (Automatic Test Vector Generation)
Security Links
There are several security links to disable reading logic from the array, and to disable JTAG access to the
device. Programming these optional links completely disables access to the device from the outside world and
provides an extra level of design security not possible in SRAM-based FPGAs. The option to program these
links is selectable through QuickWorks in the Tools/Options/Device Programming window in SpDE.
Power-Up Loading Link
The flexibility link enables Power-Up Loading of the Embedded RAM blocks. If the link is programmed, the
Power-Up Loading state machine is activated during power-up of the device. The state machine communicates
with an external EPROM via the JTAG pins to download memory contents into the on-chip RAM. If the link
is not programmed, Power-Up Loading is not enabled and the JTAG pins function as they normally would.
The option to program this link is selectable through QuickWorks in the Tools/Options/Device Programming
window in SpDE. For more information on Power-Up Loading, see QuickLogic Application Note 55 at
. See the Power-Up Loading power-up sequencing
requirement for proper functionality in Figure 16.
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