參數(shù)資料
型號: QL8150-7PT280C
廠商: QUICKLOGIC CORP
元件分類: FPGA
英文描述: FPGA, 640 CLBS, 188946 GATES, PBGA280
封裝: 0.80 MM PITCH, LFBGA-280
文件頁數(shù): 6/96頁
文件大?。?/td> 1607K
代理商: QL8150-7PT280C
2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
14
Clock Networks
Global Clocks
There are eight global clock networks in each QL8325 and QL8250 device, and five global clock networks in
each QL8150, QL8050 and QL8025 device. Global clocks can drive logic cells and I/O registers, ECUs, and
RAM blocks in the device. All global clocks have access to a Quad Net (local clock network) connection with
a programmable connection to the logic cell’s register clock input.
Figure 11: Global Clock Architecture
Quad-Net Network
There are five Quad-Net local clock networks in each quadrant for a total of 20 in a device. Each Quad-Net is
local to a quadrant. Before driving the column clock buffers, the quad-net is driven by the output of a mux
which selects between the CLK pin input and an internally generated clock source (see Figure 12).
Figure 12: Global Clock Structure
Quad Net
CLK Pin
Global Clock Net
Internally generated clock, or
clock from general routing network
Global Clock
(CLK) Input
Quad-Net Clock Network
FF
Global Clock Buffer
相關PDF資料
PDF描述
QL8150-7PT280I FPGA, 640 CLBS, 188946 GATES, PBGA280
QL8150-7PT280M FPGA, 640 CLBS, 188946 GATES, PBGA280
QL8150-7PTN280C FPGA, 640 CLBS, 188946 GATES, PBGA280
QL8150-7PTN280I FPGA, 640 CLBS, 188946 GATES, PBGA280
QL8150-7PTN280M FPGA, 640 CLBS, 188946 GATES, PBGA280
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