參數(shù)資料
型號(hào)： QL8150-7PT280C
廠商： QUICKLOGIC CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 640 CLBS, 188946 GATES, PBGA280
封裝： 0.80 MM PITCH, LFBGA-280
文件頁(yè)數(shù)： 38/96頁(yè)
文件大?。?/td> 1607K
代理商： QL8150-7PT280C
2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
43
Power vs. Operating Frequency
The basic power equation which best models power consumption is given below:
PTOTAL = 0.350 + f[0.0031 ηLC + 0.0948 ηCKBF + 0.01 ηCLBF + 0.0263 ηCKLD +
0.543 ηRAM + 0.20 ηPLL + 0.0035 ηINP + 0.0257 ηOUTP] (mW)
Where:
η
LC is the total number of logic cells in the design
η
CKBF = # of clock buffers
η
CLBF = # of column clock buffers
η
CKLD = # of loads connected to the column clock buffers
η
RAM = # of RAM blocks
η
PLL = # of PLLs
η
INP is the number of input pins
η
OUTP is the number of output pins
NOTE: To learn more about power consumption, see QuickLogic Application Note 60 at
Power-up Sequencing
Figure 43: Power-Up Sequencing
When powering up a device, the V
CC/VCCIO/VDED/VDED2 rails must take 400 s or longer to reach the
maximum value (refer to Figure 43).
NOTE: Ramping V
CC, VCCIO, VPUMP, VDED, or VDED2 faster than 400 s can cause the device to behave
improperly.
For users with a limited power budget, ensure V
CCIO, VDED, VDED2, and VPUMP are within 500 mV of VCC when
ramping up the power supplies.
Vol
ta
g
e
V
CCIO
V
DED
DED2
V
PUMP
V
CC
|V
CCIO , VDED , VDED2 , VPUMP - VCC|MAX
Time
400 us
V
CC
相關(guān)PDF資料
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