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參數(shù)資料
| 型號(hào)： | QL6250E-8PQ208C |
| 廠(chǎng)商： | QUICKLOGIC CORP |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 960 CLBS, 248160 GATES, PQFP208 |
| 封裝： | 28 X 28 MM, 3.35 MM HEIGHT, MS-028, PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 7/64頁(yè) |
| 文件大小： | 850K |
| 代理商： | QL6250E-8PQ208C |
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2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
15
Joint Test Access Group (JTAG) Information
Figure 14: JTAG Block Diagram
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, one
problem being the accessibility of test points. JTAG formed in response to this challenge, resulting in IEEE
standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture.
The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of
a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with
the Instruction Register (IR), which allow users to run three required tests along with several user-defined tests.
JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests
for fuller verification of higher level system elements.
The 1149.1 standard requires the following three tests:
Extest Instruction. The Extest Instruction performs a printed circuit board (PCB) interconnect test. This
test places a device into an external boundary test mode, selecting the boundary scan register to be
connected between the TAP Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are
preloaded with test patterns (through the Sample/Preload Instruction), and input boundary cells capture the
input data for analysis.
Sample/Preload Instruction. The Sample/Preload Instruction allows a device to remain in its functional
mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this
test, the boundary scan register can be accessed through a data scan operation, allowing users to sample
the functional data entering and leaving the device.
TCK
TMS
TRSTB
RDI
TDO
Instruction Decode
&
Control Logic
Tap Controller
State Machine
(16 States)
Instruction Register
Boundary-Scan Register
(Data Register)
Mux
Bypass
Register
Mux
Internal
Register
I/O Registers
User Defined Data Register
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| QL6250E-8PS484I | FPGA, 960 CLBS, 248160 GATES, PBGA484 |
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