參數(shù)資料
型號(hào)： QL6250E-8PQ208C
廠商： QUICKLOGIC CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 960 CLBS, 248160 GATES, PQFP208
封裝： 28 X 28 MM, 3.35 MM HEIGHT, MS-028, PLASTIC, QFP-208
文件頁(yè)數(shù)： 45/64頁(yè)
文件大小： 850K
代理商： QL6250E-8PQ208C
2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
5
Embedded Computational Unit (ECU)
Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively—
these functions require high logic cell usage while garnering only moderate performance results.
The Eclipse-E architecture allows for functionality above and beyond that achievable using programmable logic
devices. By embedding a dynamically reconfigurable computational unit, the Eclipse-E device can address
various arithmetic functions efficiently. This approach offers greater performance and utilization than
traditional programmable logic implementations. The embedded block is implemented at the transistor level
as shown in Figure 5.
Figure 5: ECU Block Diagram
The Eclipse-E ECU block (Table 3) is placed next to the SRAM circuitry for efficient memory/instruction fetch
and addressing for DSP algorithmic implementations.
Up to twelve 8-bit MAC functions can be implemented per cycle for a total of up to 1.2 billion MACs/s when
clocked at 100 MHz. Additional multiply-accumulate functions can be implemented in the programmable logic.
Table 3: Eclipse-E ECU Block
Device
ECUs
QL6250E
10
QL6325E
12
A[0:15]
B[0:15]
SIGN2
SIGN1
CIN
S1
S2
S3
A
B
C
D
3-4
decoder
8-bit
Multiplier
16-bit
Adder
17-bit
Register
2-1
mux
2-1
mux
3-1
mux
Q[16:0]
CLK
RESET
DQ
00
01
10
A[7:0]
A[15:8]
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