參數(shù)資料
型號(hào): QL6250E-7PQ208C
廠(chǎng)商: QUICKLOGIC CORP
元件分類(lèi): FPGA
英文描述: FPGA, 960 CLBS, 248160 GATES, PQFP208
封裝: 28 X 28 MM, 3.35 MM HEIGHT, MS-028, PLASTIC, QFP-208
文件頁(yè)數(shù): 32/64頁(yè)
文件大小: 850K
代理商: QL6250E-7PQ208C
2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
38
Power-Up Sequencing
Figure 41: Power-Up Sequencing
When powering up a device, the V
CCPLL/VCC/VCCIO/VDED/VDED2 rails must take 400 s or longer to reach
the maximum value (refer to Figure 41).
NOTE: Ramping V
CCPLL, VCC, VCCIO, VPUMP, VDED, or VDED2 faster than 400 s can cause the device to
behave improperly.
For users with a limited power budget, ensure V
CCIO, VDED, VDED2, and VPUMP are within 500 mV of VCC when
ramping up the power supplies.
Vo
lt
ag
e
V
CCIO
V
DED
V
DED2
V
PUMP
V
CC
|V
CCIO, VDED, VDED2, VPUMP - VCC|MAX
Time
400 us
V
CC
V
ccPLL
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