參數(shù)資料
型號(hào)： QL5842-33APS484I
廠商： QUICKLOGIC CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA484
封裝： 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAJ-1, BGA-484
文件頁(yè)數(shù)： 2/76頁(yè)
文件大?。?/td> 1128K
代理商： QL5842-33APS484I
2007 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. L
10
Process Data
The QL58x2 device family is fabricated on a 0.18
μ, six layer metal CMOS process. The core voltage is 1.8 V
and the I/Os are up to 3.3 V drive/tolerant. The QL58x2 device family product line is available in commercial,
industrial, and military temperature grades.
Programmable Logic Architectural Overview
The QL58x2 device family logic cell structure is presented in Figure 3. This architectural feature addresses
today's register-intensive designs.
The QL58x2 device family logic cell structure presented in Figure 3 is a dual register, multiplexer-based logic
cell. It is designed for wide fan-in and multiple, simultaneous output functions. Both registers share CLK, SET,
and RESET inputs. The second register has a two-to-one multiplexer controlling its input. The register can be
loaded from the NZ output or directly from a dedicated input.
NOTE: The input PP is not an “input” in the classical sense. It is a static input to the logic cell and selects
which path (NZ or PS) is used as an input to the Q2Z register. All other inputs are dynamic and can be
connected to multiple routing channels.
The complete logic cell consists of two six-input AND gates, four two-input AND gates, seven two-to-one
multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30
(including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six
outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell
accommodates many user functions with a single level of logic delay while other architectures require two or
more levels of delay.
Table 8: Performance Standardsa
a. Performance standards for worst-case commercial conditions.
Function
Description
Slowest Speed Grade
Fastest Speed Grade
Multiplexer
16:1
2.8 ns
2.4 ns
Parity Tree
24
3.4 ns
2.9 ns
36
4.6 ns
3.9 ns
Counter
16 bit
275 MHz
328 MHz
32 bit
250 MHz
300 MHz
Synchronous
FIFO
128 x 32
197 MHz
235 MHz
128 x 64
188 MHz
266 MHz
256 x 16
208 MHz
248 MHz
Clock-to-Out
6.5 ns
6 ns
System clock
200 MHz
300 MHz
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