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參數(shù)資料
| 型號： | QL5810-66CPTN196I |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA196 |
| 封裝： | 12 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MO-216C, TFBGA-196 |
| 文件頁數(shù)： | 12/80頁 |
| 文件大?。?/td> | 1125K |
| 代理商： | QL5810-66CPTN196I |
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2006 QuickLogic Corporation
QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. L
2
Architecture Overview
The QL58x0 device family of QuickPCI Embedded Standard Products (ESPs) provides a complete and
customizable PCI interface solution combined with programmable logic. Since the QL58x0 devices provide
optimized pre-verified PCI cores, the burden of PCI timing closure and PCI protocol compliance has been
eliminated and allows for the maximum 32-bit PCI bus bandwidth (264 MBps).
The programmable logic portion of this family contains up to 1,478 QuickLogic Logic Cells and up to 22
QuickLogic Dual-Port RAM Blocks. These configurable RAM blocks can be configured in many width/depth
combinations. They can also be combined with logic cells to form FIFOs, or be initialized via Serial EEPROM
on power-up and used as ROMs.
The QL58x0 device meets PCI 2.3 electrical and timing specifications and has been fully hardware-tested. The
QL58x0 device features 1.8 V operation with multi-volt compatible I/Os. The device can easily operate in
3.3 V embedded systems and is fully compatible with 3.3 V applications.
PCI Controller
The PCI Controller is a 33/66 MHz 32-bit PCI 2.3 compliant Target Controller capable of infinite length
Target Write and Read transactions at zero wait states (264 MBps).
The Target interface offers full PCI Configuration Space and flexible target addressing. It supports zero-wait-
state target Write and Read operations. It also supports retry, disconnect with/without data transfer, and target
abort requested by the back end. Any number of 32-bit BARs may be configured as either memory or I/O
space. All required and optional PCI 2.3 Configuration Space registers can be implemented within the
programmable region of the device. A reference design of a Target Configuration Space and Addressing
module is available and is included in the QuickWorks design software.
The interface ports are designed for target transactions. The Target Configuration Space and Address
Decoding are done in the programmable logic region of the device. These functions are not timing critical, so
leaving these elements in the programmable region allows the greatest degree of flexibility to the designer.
Table 1 shows several commonly implemented IP cores in the programmable logic portion of the Target
Controller device. Their respective logic cell utilization and performance information are shown for easy
reference. Notice that the Configuration Space and Address Decoding core is labelled as an essential IP core.
This IP block is necessary for the Target Controller to be fully functional. The optional IP cores are common
interface IP cores made available so that designers may implement according to their design requirements.
These optional IP cores do not affect the functionality of the Target Controller.
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