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| 型號： | QL3040-0PQ208I |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | 40000 usable PLD gate pASIC 3 FPGA combining High performance and high density |
| 中文描述： | FPGA, 1008 CLBS, 40000 GATES, 225 MHz, PQFP208 |
| 封裝： | 28 X 28 MM, 3.35 MM HEIGHT, PLASTIC, MS-029, QFP-208 |
| 文件頁數(shù)： | 34/49頁 |
| 文件大?。?/td> | 885K |
| 代理商： | QL3040-0PQ208I |
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www.quicklogic.com
2005 QuickLogic Corporation
pASIC 3 FPGA Family Data Sheet Rev. D
4
Electrical Specifications
AC Characteristics at V
CC = 3.3 V, TA = 25°C (K = 1.00)
To calculate delays, multiply the appropriate K factor from Table 9 by the numbers provided in Table 3
through Table 7.
Table 3: Logic Cells
Symbol
Parameter
Propagation Delays (ns) Fanouta
a. Stated timing for worst case Propagation Delay over process variation at V
CC = 3.3 V and TA = 25°C. Multiply by the appropriate
Delay Factor, K, for speed grade, voltage, and temperature settings as specified in
1
2
3
4
8
tPD
Combinatorial Delay b
b. These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net
delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
1.41.7
1.92.2
3.2
tSU
Setup Time b
1.7
tH
Hold Time
0.0
tCLK
Clock to Q Delay
0.7
1.0
1.2
1.5
2.5
tCWHI
Clock High Time
1.2
tCWLO
Clock Low Time
1.2
tSET
Set Delay
1.0
1.3
1.5
1.8
2.8
tRESET
Reset Delay
0.8
1.1
1.3
1.6
2.6
tSW
Set Width
1.9
tRW
Reset Width
1.8
Table 4: Input-Only/Clock Cells
Symbol
Parameter
Propagation Delays (ns) Fanout a
a. Stated timing for worst case Propagation Delay over process variation at V
CC = 3.3 V and TA = 25°C. Multiply by the appropriate
Delay Factor, K, for speed grade, voltage, and temperature settings as specified in
1
2
3
4
8
12
24
tIN
High Drive Input Delay
1.5
1.6
1.8
1.9
2.4
2.9
4.4
tINI
High Drive Input, Inverting Delay
1.6
1.7
1.9
2.0
2.5
3.0
4.5
tISU
Input Register Set-Up Time
3.1
tIH
Input Register Hold Time
0.0
tlCLK
Input Register Clock To Q
0.7
0.8
1.0
1.1
1.6
2.1
3.6
tlRST
Input Register Reset Delay
0.6
0.7
0.9
1.0
1.5
2.0
3.5
tlESU
Input Register clock Enable Set-Up Time
2.3
tlEH
Input Register Clock Enable Hold Time
0.0
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