
PEB 2023
PEF 2023
Functional Description
Semiconductor Group
16
08.97
2
Functional Description
The PEB/F 2023 contains the following functional blocks:
Supply and Biasing
Undervoltage Detection
Temperature Compensated Voltage Reference
Sawtooth Oscillator
Error Amplifier
Pulse Width Modulator
Digital Current Limiting
Soft Start
Control Logic (double pulse inhibit)
Output Driver
The reference voltage provides 4V for the regulation loop. A high gain error amplifier
compares the reference voltage to the output voltage. The output of the error amplifier is
then compared to a periodic ramp, which is generated by the sawtooth-oscillator circuit.
The comparator output is a fixed-frequency, variable pulse width logic signal, which
passes through logic circuits and the output driver and out to the external high voltage
power-switching-FET.
A digital current limiting device suppresses the PWM logic signal when the voltage
difference between current limit sense input I
P
and GND reaches 100 mV to protect the
external power-switching-FET.
Non-isolated and isolated SMPS-configurations are possible. Logic and analog circuits
are implemented in BICMOS in order to achieve low power dissipation.
Start-Up Procedure
Before the switched-mode DC/DC converter starts, a sequence of several conditions has
to be passed in order to avoid any system malfunction.
An integrated 6V linear voltage regulator supplies the internal low-voltage BICMOS-
circuits from the input voltage V
S
. The generated supply voltage is connected to pin V
EXT
and has to be buffered by an external capacitor (C
min
= 1
μ
F). Power dissipation of the
linear voltage regulator can be reduced, if an external supply is used for that purpose by
connecting it to pin V
EXT
. If the input voltage at V
EXT
is greater than 6.2V, the internal
linear voltage regulator turns off and the internal BICMOS-circuits are then fed from the
external voltage source (power housekeeping input V
EXT
). In this case, the input current
at V
EXT
is approximately 0.6mA.