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| 型號(hào)： | Q67121C2168A1 |
| 英文描述： | IC-SM-16 BIT CPU |
| 中文描述： | 集成電路的Sm - 16位CPU |
| 文件頁數(shù)： | 56/121頁 |
| 文件大小： | 1000K |
| 代理商： | Q67121C2168A1 |
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Semiconductor Group
6-22
On-Chip Peripheral Components
C501
6.2.2
Timer/Counter 2
Timer 2 is a 16-bit timer / counter which can operate as timer or counter. It has three operating
modes:
– 16-bit auto-reload mode (up or down counting)
– 16-bit capture mode
– Baudrate generator for the serial interface
The modes are selected by bits in the SFR T2CON (C8H) as shown in
table 6-6
:
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the timer function, the TL2 register is
incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count
rate is 1/12 of the oscillator frequency.
In the counter function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T2 (P1.0). In this function, the external input is sampled during
S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next
cycle, the count is incremented. The new value appears in the register during S3P1 of the cycle
following the one in which the transition was detected. Since it takes two machine cycles to
recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscilllator frequency. To ensure
that a given level is sampled at least once before it changes, it should be held for at least one full
machine cycle.
Table 6-6
Timer/Counter 2 - Operating Modes
RXCLK + TXCLK
CP/RL2
TR2
Mode
0
0
1
16-bit auto-reload
0
1
1
16-bit capture
1
X
1
Baud rate generator
X
X
0
(OFF)
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