參數(shù)資料
型號(hào): Q67121C2168A1
英文描述: IC-SM-16 BIT CPU
中文描述: 集成電路的Sm - 16位CPU
文件頁(yè)數(shù): 55/121頁(yè)
文件大?。?/td> 1000K
代理商: Q67121C2168A1
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Semiconductor Group
6-21
On-Chip Peripheral Components
C501
6.2.1.5
Mode 3
Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. The
effect is the same as setting TR1=0. Timer 0 in mode 3 establishes TL0 and TH0 as two seperate
counters. The logic for mode 3 on timer 0 is shown in
figure 6-14
. TL0 uses the timer 0 control bits:
C/T, Gate, TR0, INT0 and TF0. TH0 is locked into a timer function (counting machine cycles) and
takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls the “timer 1” interrupt.
Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When timer 0 is in
mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still
be used by the serial channel as a baud rate generator, or in fact, in any application not requiring
an interrupt from timer 1 itself.
Figure 6-14
Timer/Counter 0, Mode 3: Two 8-Bit Timers/Counters
MCS02096
1
&
OSC
C/T = 0
TL0
(8 Bits)
TF0
C/T = 1
TR1
Gate
P3.2/INT0
Control
Interrupt
(8 Bits)
TH0
Interrupt
TF1
Control
TR1
/12
f
OSC
OSC
f
/12
P3.4/T0
÷ 12
=1
<
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