參數(shù)資料
型號(hào): Q67060-S7411-A803
廠商: INFINEON TECHNOLOGIES AG
元件分類: 通用總線功能
英文描述: High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs 16-TSSOP -55 to 125
中文描述: 智能阻抗高側(cè)電源開關(guān)
文件頁數(shù): 6/16頁
文件大?。?/td> 262K
代理商: Q67060-S7411-A803
Data sheet BTS 6143 D
Parameter and Conditions
at
T
j
= 25,
V
bb
= 12 V unless otherwise specified
Symbol
Values
typ
Unit
min
max
Infineon Technologies AG
6 of 16
2003-Oct-01
Diagnostic Characteristics
Current sense ratio, static on-condition
k
ILIS
=
I
L
:
I
IS
,
I
IS
<
I
IS,lim
16)
,
V
IS
<
V
OUT
-
5
V,
V
bIN
>
4.5
V
k
ILIS
--
10 000
--
IL = 30A, Tj = -40°C:
Tj = +25°C:
Tj = +150°C:
IL = 7.5A, Tj = -40°C:
Tj = +25°C:
Tj = +150°C:
IL = 2.5A, Tj = -40°C:
Tj = +25°C:
Tj = +150°C:
IL = 0.5A, Tj = -40°C:
Tj = +25°C:
Tj = +150°C:
8300
8300
8300
7500
8000
8200
7100
7700
8000
5000
5500
6000
10000
9700
9300
10000
9700
9300
10000
9700
9300
12000
12000
12000
11000
10600
10000
11400
10800
10200
13400
12500
12000
21000
19000
18000
I
IN
= 0
(e.g. during deenergizing of inductive loads)
:
Sense current under fault conditions
17)
VON>1V, typ
Sense saturation current
VON<1V, typ
Fault-Sense signal delay after input current positive
slope, V
ON
>1V,
T
j = -40...+150°C
Current sense leakage current,
I
IN
=
0
Current sense offset current,
V
IN
=
0,
I
L
0
Minimum load current for sense functionality,
V
IN
=
0,
T
j = -40...+150°C
Current sense settling time to
I
IS static
after input
current positive slope,
18
)
I
L
= 0
20 A,
T
j
= -40...+150°C
Current sense settling time during on condition,
18)
I
L
= 10
20 A,
T
j
= -40...+150°C
Overvoltage protection
I
bb
=
15
mA
--
0
--
T
j
=
-40...+150°C:
I
IS,fault
I
IS,lim
t
delay(fault)
4.0
5.2
7.5
mA
T
j
=
-40...+150°C:
4.0
350
6.0
650
7.5
mA
μ
s
1200
I
IS(LL)
I
IS(LH)
I
L(MIN)
--
0.1
0.5
μ
A
μ
A
mA
--
0.1
1
50
--
--
t
son(IS)
--
250
500
μ
s
t
slc(IS)
V
Z,IS
--
50
100
μ
s
T
j
=
-40...+150°C:
63
67
--
V
16)
See also figures 4.x and 6.x on page 13 and 14.
17)
Fault conditions are overload during on (i.e. V
ON
>1V typ.), overtemperature and short circuit; see also truth
table on page 8.
18
) not subject to production test, specified by design
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