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參數(shù)資料
| 型號(hào)： | Q67060-S6302-A3 |
| 廠商： | SIEMENS AG |
| 英文描述： | High Speed CMOS Logic Dual 4-Stage Static Shift Registers 16-PDIP -55 to 125 |
| 中文描述： | 智能雙通道阻抗高側(cè)電源開(kāi)關(guān) |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 191K |
| 代理商： | Q67060-S6302-A3 |
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BTS 611 L1
Semiconductor Group
2
Pin
1
2
3
4
Symbol
OUT1 (Load, L)
GND
IN1
Vbb
Function
Output 1, protected high-side power output of channel 1
Logic ground
Input 1, activates channel 1 in case of logical high signal
Positive power supply voltage,
the tab is shorted to this pin
Diagnostic feedback: open drain, low on failure
5
6
7
ST
IN2
OUT2 (Load, L)
Input 2, activates channel 2 in case of logical high signal
Output 2, protected high-side power output of channel 2
Maximum Ratings
at T
j
= 25 °C unless otherwise specified
Parameter
Supply voltage (overvoltage protection see page 4)
Supply voltage for full short circuit protection
T
j Start
=-40 ...+150°C
Load dump protection
2
)
V
LoadDump
= U
A
+ V
s
, U
A
= 13.5 V
R
I
3
)
= 2
, R
L
= 5.3
, t
d
= 200 ms, IN= low or high
Load current (Short circuit current, see page 5)
Operating temperature range
Storage temperature range
Power dissipation (DC), T
C
≤
25 °C
Inductive load switch-off energy dissipation, single pulse
V
bb
=
12V, T
j,start
=
150°C, T
C
=
150°C const.
one channel, I
L
=
2.3
A, Z
L
=
89
mH, 0
:
both channels parallel, I
L
=
4.4
A, Z
L
=
47
mH, 0
:
see diagrams on page 9
Electrostatic discharge capability (ESD)
(Human Body Model)
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
Input voltage (DC)
Current through input pin (DC)
Current through status pin (DC)
see internal circuit diagrams page 7
Symbol
V
bb
V
bb
Values
Unit
43
34
V
V
V
Load dump4
)
60
V
I
L
T
j
T
stg
P
tot
self-limited
-40 ...+150
-55 ...+150
A
°C
36
W
E
AS
290
580
mJ
IN:
all other pins:
V
ESD
1.0
2.0
kV
V
IN
I
IN
I
ST
-10 ... +16
V
±
2.0
±
5.0
mA
2
)
Supply voltages higher than V
bb(AZ)
require an external current limit for the GND and status pins, e.g. with a
150
resistor in the GND connection and a 15 k
resistor in series with the status pin. A resistor for the
protection of the input is integrated.
3)
R
I
= internal resistance of the load dump test pulse generator
4)
V
Load dump
is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
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|---|---|
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