參數(shù)資料
型號： PXAS37KFBE
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range
中文描述： 16-BIT, OTPROM, 30 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁數(shù)： 38/52頁
文件大小： 295K
代理商： PXAS37KFBE
Philips Semiconductors
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I
2
C, 2 UARTs, 16 MB address range
Preliminary specification
XA-S3
2000 Dec 01
38
AC ELECTRICAL CHARACTERISTICS (5 V)
V
DD
= 4.5 V to 5.5 V; T
amb
= 0 to +70
°
C for commercial, T
amb
= –40
°
C to +85
°
C for industrial.
SYMBOL
FIGURE
PARAMETER
LIMITS
UNIT
MIN
MAX
External Clock
f
C
t
C
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Address Cycle
32
Oscillator frequency
0
30
MHz
32
Clock period and CPU timing cycle
1/f
C
t
C
* 0.5
t
C
* 0.4
ns
32
Clock high-time (Note 7)
ns
32
Clock low time (Note 7)
ns
32
Clock rise time (Note 7)
5
ns
32
Clock fall time (Note 7)
5
ns
t
LHLL
t
AVLL
t
LLAX
Code Read Cycle
26, 28, 30
ALE pulse width (programmable)
(V1 * t
C
) – 6
(V1 * t
C
) – 12
(t
C
/2) – 10
ns
26, 28, 30
Address valid to ALE de-asserted (set-up)
ns
26, 28, 30
Address hold after ALE de-asserted
ns
t
PLPH
t
LLPL
t
AVIVA
t
AVIVB
t
PLIV
t
PHIX
t
PHIZ
t
IXUA
Data Read Cycle
26
PSEN pulse width
(V2 * t
C
) – 10
(t
C
/2) – 7
ns
26
ALE de-asserted to PSEN asserted
ns
26
Address valid to instruction valid, ALE cycle (access time)
(V3 * t
C
) – 36
(V4 * t
C
) – 29
(V2 * t
C
) – 29
ns
27
Address valid to instruction valid, non-ALE cycle (access time)
ns
26
PSEN asserted to instruction valid (enable time)
ns
26
Instruction hold after PSEN de-asserted
0
ns
26
Bus 3-State after PSEN de-asserted
t
C
– 8
ns
26
Hold time of unlatched part of address after instruction latched
0
ns
t
RLRH
t
LLRL
t
AVDVA
t
AVDVB
t
RLDV
t
RHDX
t
RHDZ
t
DXUA
Data Write Cycle
28
RD pulse width
(V7 * t
C
) – 10
(t
C
/2) – 7
ns
28
ALE de-asserted to RD asserted
ns
28
Address valid to data input valid, ALE cycle (access time)
(V6 * t
C
) – 36
(V5 * t
C
) – 29
(V7 * t
C
) – 29
ns
29
Address valid to data input valid, non-ALE cycle (access time)
ns
28
RD low to valid data in (enable time)
ns
28
Data hold time after RD de–asserted
0
ns
28
Bus 3-State after RD de-asserted (disable time)
t
C
– 8
ns
28
Hold time of unlatched part of address after data latched
0
ns
t
WLWH
t
LLWL
t
QVWX
t
WHQX
t
AVWL
t
UAWH
Wait Input
30
WR pulse width
(V8 * t
C
) – 10
(V12 * t
C
) – 10
(V13 * t
C
) – 22
(V11 * t
C
) – 5
(V9 * t
C
) – 22
(V11 * t
C
) – 7
ns
30
ALE falling edge to WR asserted
ns
30
Data valid before WR asserted (data set-up time)
ns
30
Data hold time after WR de-asserted (Note 6)
ns
30
Address valid to WR asserted (address set-up time) (Note 5)
ns
30
Hold time of unlatched part of address after WR is de-asserted
ns
t
WTH
t
WTL
31
WAIT stable after bus strobe (RD, WR, or PSEN) asserted
(V10 * t
C
) – 30
ns
31
WAIT hold after bus strobe (RD, WR, or PSEN) asserted
(V10 * t
C
) – 5
ns
NOTES ON PAGE 41.
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