參數(shù)資料
型號： PXAS37KFBE
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range
中文描述： 16-BIT, OTPROM, 30 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁數(shù)： 35/52頁
文件大?。?/td> 295K
代理商： PXAS37KFBE
Philips Semiconductors
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I
2
C, 2 UARTs, 16 MB address range
Preliminary specification
XA-S3
2000 Dec 01
35
8-BIT MODE A/D CONVERTER DC ELECTRICAL CHARACTERISTICS
T
amb
= 0 to +70
°
C for commercial, T
amb
=
–40 to +85
°
C for industrial, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
MIN
MAX
AV
DD
AI
DD
AI
ID
AI
PD
Analog supply voltage
2.7
3.3
V
Analog supply current (operating)
Port 5 = 0 to AV
DD
2.5
mA
Analog supply current (Idle mode)
2.5
μ
A
μ
A
μ
A
Analog supply current (Power-Down mode)
Commercial temperature range
100
Industrial temperature range
150
AV
IN
R
REF
C
IA
DL
e
IL
e
OS
e
G
e
A
e
M
CTC
C
t
NOTES:
1. Conditions: AV
REF–
= 0 V; AV
REF+
= 3.07 V.
2. The differential non-linearity (DL
e
) is the difference between the actual step width and the ideal step width. See Figure 25.
3. The ADC is monotonic, there are no missing codes.
4. The integral non-linearity (IL
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 25.
5. The offset error (OS
) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
the straight line which fits the ideal transfer curve. See Figure 25.
6. The gain error (G
e
) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. See Figure 25.
7. The absolute voltage error (A
e
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve.
8. This should be considered when both analog and digital signals are input simultaneously to Port 5. Parameter is guaranteed by design.
Analog input voltage
AV
SS
–0.2
125
AV
DD
+0.2
225
V
Resistance between V
REF+
and V
REF–
Analog input capacitance
Differential non-linearity
1, 2, 3
Integral non-linearity
1, 4
Offset error
1, 5
Gain error
1, 6
Absolute voltage error
1, 7
k
15
pF
±
1
±
1
±
2.5
±
1
±
3
±
1
LSB
LSB
LSB
%
LSB
Channel-to-channel matching
Crosstalk between inputs of port
8
LSB
0 – 100 kHz
–60
dB
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