參數(shù)資料
型號： PXAS37KFA512
英文描述： IC-SM-16-BIT MCU
中文描述： 集成電路釤16位MCU
文件頁數(shù)： 39/51頁
文件大?。?/td> 405K
代理商： PXAS37KFA512
Philips Semiconductors
XA 16-bit microcontroller
32K/1K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I
2
C, 2 UARTs, 16 MB address range
Preliminary specification
XA-S3
2000 Mar 09
39
AC ELECTRICAL CHARACTERISTICS (5 V RANGE)
(continued)
This set of parameters is referenced to the XA-S3 clock output.
SYMBOL
FIGURE
PARAMETER
LIMITS
UNIT
MIN
MAX
Address Cycle
t
CHLH
t
CLLL
t
CHAV
t
CHAX
Code Read Cycle
26
CLKOUT rising edge to ALE rising edge
–
13
ns
26
CLKOUT falling edge to ALE falling edge
–
9
ns
26
CLKOUT rising edge to address valid
–
18
ns
26
CLKOUT rising edge to address changing (hold time)
2
–
ns
t
CHPL
t
CHPH
t
IVCH
t
CHIX
t
CHIZ
Data Read Cycle
26
CLKOUT rising edge to PSEN asserted
–
14
ns
26
CLKOUT rising edge to PSEN de-asserted
–
12
ns
26
Instruction valid to CLKOUT rising edge (setup time)
20
–
ns
26
CLKOUT rising edge to instruction changing (hold time)
0
–
ns
26
CLKOUT rising edge to Bus 3-State (code read)
–
t
C
–8
ns
t
CHRL
t
CHRH
t
DVCH
t
CHDX
t
CHDZ
Data Write Cycle
28
CLKOUT rising edge to RD asserted
–
12
ns
28
CLKOUT rising edge to RD de-asserted
–
10
ns
28
Data valid to CLKOUT rising edge (setup time)
20
–
ns
28
CLKOUT rising edge to Data changing (hold time)
0
–
ns
28
CLKOUT rising edge to Bus 3-State (data read)
–
t
C
–8
ns
t
CHWL
t
CHWH
t
QVCH
t
CHQX
Wait Input
30
CLKOUT falling edge to WR asserted
–
12
ns
30
CLKOUT rising edge to WR de-asserted
–
10
ns
30
Data valid to CLKOUT rising edge (setup time)
4
–
ns
30
CLKOUT rising edge to Data changing (hold time)
0
–
ns
t
CHWTH
NOTES ON PAGE 41.
31
WAIT valid prior to CLKOUT rising edge
8
21
4
ns
Next
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