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| 型號： | PWL6030B1AECMR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA187 |
| 封裝： | 7 X 7 MM, 0.40 MM PITCH, GREEN, FCBGA-187 |
| 文件頁數(shù)： | 84/97頁 |
| 文件大?。?/td> | 937K |
| 代理商： | PWL6030B1AECMR |
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SWCS045-025
SDA
SCL
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SWCS045B
– SEPTEMBER 2010 – REVISED JUNE 2011
The device replies by sending a fourth byte representing the content of the internal registers, starting at the base
address and next consecutive ones.
Figure 27 shows a multiple-byte read access.
Figure 27. I2C Read Access Multiple Bytes
Secure Registers
Some registers of the TWL6030 device can be protected by restricting their access in write mode to software
running in the secure mode of the host read access to protected registers. Secure access is enabled or disabled
by the MSECURE control signal.
The following components or actions can be protected:
All RTC registers
64 bits of general-purpose memory (8 x 8) in the backup domain named VALIDITY
The read accesses are independent to the MSECURE value.
When MSECURE is logical level 1, all read and write accesses are authorized; when MSECURE is logical level
0, only read accesses are authorized.
This security feature (MSECURE detection) is enabled and disabled by an EPROM bit.
Interrupts
The INT signal (active low) warns the host processor of any event occurring on the TWL6030 device. The host
processor then pools the interrupt from the interrupt status register through I2C to identify the interrupt source.
Each interrupt source can be individually masked through the interrupt mask line registers and mask status
registers.
If interrupts occur while the status registers are not cleared, the status registers are not updated immediately.
Instead, the interrupts are held pending in a second stage of shadow registers, waiting for all previous interrupts
to be cleared first. When the interrupt line goes low again, operated just after the first set of interrupts clear, all
status registers are updated with those pending interrupt sources, coming directly from the shadow registers.
To clear both interrupts and register status, a write in the status registers must be done. Each write has the same
effect (interrupt line goes high and all status registers are cleared). This implies that the interrupt subroutine
acquires the three status registers before acknowledging the interrupt to avoid losing any interrupt sources.
NOTE
An interrupt associated with a function should be masked before enabling or disabling the
feature; otherwise, it might generate a false interrupt directly linked to the state change of the
feature and not related to an external detection event (for example, BAT_VLOW interrupt with
VBATMIN_HI comparator).
INT is always active low.
When a TWL6030 interrupt occurs:
–
Software should first read all status registers, INT_STS_A, INT_STS_B, and INT_STS_C.
–
Execute the subroutines related to the read interrupts.
–
Clear the interrupt status of all status registers
Copyright
2010–2011, Texas Instruments Incorporated
85
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