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參數(shù)資料
| 型號： | PUMA68S16000XB-015 |
| 元件分類： | SRAM |
| 英文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 15 ns, PQMA68 |
| 封裝： | 25.27 X 25.27 X 5.08 MM, PLASTIC, LCC-68 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 145K |
| 代理商： | PUMA68S16000XB-015 |
Issue 5.2 March 2001
PAGE 7
Valid Data
Address
/OE
/CS
Data In
Data Out
t
WC
tAW
t
WR(5)
t
CW(3)
t
AS(4)
tWP(2)
tDW
tDH
tOHZ(6)
High Z
High Z(8)
/WE
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ;
A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of /CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
11 ./CS=/CS1~4
Write Cycle 1
(/OE = Clock)
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