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參數(shù)資料
| 型號： | PUMA68S16000ABM-020 |
| 元件分類： | SRAM |
| 英文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 20 ns, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 124K |
| 代理商： | PUMA68S16000ABM-020 |
ISSUE 5.0 : May 2001
PUMA 68S16000/AB-020/025/35/45
6
Write Cycle No.2 Timing Waveform
Write Cycle No.2 Timing Waveform (1,5)
(1,5)
AC Write Characteristics Notes
(1) All write cycle timing is referenced from the last valid address to the first transition address.
(2) All writes occur during the overlap of CS1~4 and WE low.
(3) If OE, CS1~4, and WE are in the Read mode during this period, the I/O pins are low impedance state.
Inputs of opposite phase to the output must not be applied because bus contention can occur.
(4) Dout is the Read data of the new address.
(5) OE is continuously low.
(6) Address is valid prior to or coincident with CS1~4 and WE low, too avoid inadvertant writes.
(7) CS1~4 or WE must be high during address transitions.
(8) When CS1~4 are low : I/O pins are in the output state. Input signals of opposite phase leading to the
output should not be applied.
(9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
t
AW
t
CW
WR(7)
WC
AS(6)
DW
DH
OH
OW
WHZ(3,9)
WP(2)
Don't
t
Address
CS1~4
WE
Dout
Din
t
Care
High-Z
(4)
(8)
Data Valid
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