PRODUCTPREVIEW
www.ti.com
SWCS046C – MARCH 2010 – REVISED JUNE 2010
7
6
5
4
3
2
1
0
ILMAX
Reserved
SEL
ST
Bits
Field Name
Description
Type
Reset
7:6
ILMAX
Select maximum load current:
RW
0x0
when 00: 0.6 A
when 01: 1.0 A
when 10: 1.0 A
when 11: 1.0 A
5:4
Reserved
Reserved bit
RO
0x0
R returns
0s
3:2
SEL
Output voltage selection (EEPROM bits):
RW
See (1)
SEL[1:0] = 00 : 1.5 V
SEL[1:0] = 01 : 1.8 V
SEL[1:0] = 10 : 2.5 V
SEL[1:0] = 11 : 3.3 V
1:0
ST
Supply state (EEPROM bits):
RW
0x0
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
(Write access available in test mode only)
(1)
The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 43. VDD1_REG
Address Offset
0x21
Physical Address
Instance
Description
VDD1 control register
Type
RW
7
6
5
4
3
2
1
0
VGAIN_SEL
ILMAX
TSTEP
ST
Bits
Field Name
Description
Type
Reset
7:6
VGAIN_SEL
Select output voltage multiplication factor: G (EEPROM bits):
RW
0x0
when 00: x1
when 01: TBD
when 10: x2
when 11: x3
5:4
ILMAX
Select maximum load current:
RW
0
when 0: 1.0 A
when 1: > 1.5 A
3:2
TSTEP
Time step: when changing the output voltage, the new value is reached
RW
0x3
through successive 12.5 mV voltage steps (if not bypassed). The
equivalent programmable slew rate of the output voltage is then:
TSTEP[2:0] = 000 : step duration is 0, step function is bypassed
TSTEP[2:0] = 001 : 12.5 mV/s (sampling 3 Mhz)
TSTEP[2:0] = 010 : 9.4 mV/s (sampling 3 Mhz × 3/4)
TSTEP[2:0] = 011 : 7.5 mV/s (sampling 3 Mhz × 3/5) (default)
TSTEP[2:0] = 100 : 6.25 mV/s(sampling 3 Mhz/2)
TSTEP[2:0] = 101 : 4.7 mV/s(sampling 3 Mhz/3)
TSTEP[2:0] = 110 : 3.12 mV/s(sampling 3 Mhz/4)
TSTEP[2:0] = 111 : 2.5 mV/s(sampling 3 Mhz/5)
1:0
ST
Supply state (EEPROM bits):
RW
0x0
ST[1:0] = 00 : Off
ST[1:0] = 01 : On, high power mode
ST[1:0] = 10 : Off
ST[1:0] = 11 : On, low power mode
Copyright 2010, Texas Instruments Incorporated
63