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SWCS046C – MARCH 2010 – REVISED JUNE 2010
7
6
5
4
3
2
1
0
HOTDIE_IT
PWRHOLD_IT
PWRON_LP_IT
PWRON_IT
VMBHI_IT
VMBDCH_IT
RTC_ALARM_IT
RTC_PERIOD_IT
Bits
Field Name
Description
Type
Reset
7
RTC_PERIOD_IT
RTC period event interrupt status.
RW
0
W1 to Clr
6
RTC_ALARM_IT
RTC alarm event interrupt status.
RW
0
W1 to Clr
5
HOTDIE_IT
Hot die event interrupt status.
RW
0
W1 to Clr
4
PWRHOLD_IT
PWRHOLD event interrupt status.
RW
0
W1 to Clr
3
PWRON_LP_IT
PWRON Long Press event interrupt status.
RW
0
W1 to Clr
2
PWRON_IT
PWRON event interrupt status.
RW
0
W1 to Clr
1
VMBHI_IT
VBAT > VMHI event interrupt status
RW
0
W1 to Clr
0
VMBDCH_IT
VBAT > VMBDCH event interrupt status.
RW
0
Active only if Main Battery comparator VMBCH programmable threshold
W1 to Clr
is not bypassed (VMBCH_SEL[1:0]
≠ 00)
Table 74. INT_MSK_REG
Address Offset
0x51
Physical Address
Instance
Description
Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
Type
RW
7
6
5
4
3
2
1
0
VMBHI_IT_MSK
HOTDIE_IT_MSK
PWRON_IT_MSK
VMBDCH_IT_MSK
PWRHOLD_IT_MSK
PWRON_LP_IT_MSK
RTC_ALARM_IT_MSK
RTC_PERIOD_IT_MSK
Bits
Field Name
Description
Type
Reset
7
RTC_PERIOD_IT_MS RTC period event interrupt mask.
RW
0
K
6
RTC_ALARM_IT_MS
RTC alarm event interrupt mask.
RW
0
K
5
HOTDIE_IT_MSK
Hot die event interrupt mask.
RW
0
4
PWRHOLD_IT_MSK
PWRHOLD rising edge event interrupt mask.
RW
0
3
PWRON_LP_IT_MSK
PWRON Long Press event interrupt mask.
RW
0
2
PWRON_IT_MSK
PWRON event interrupt mask.
RW
0
Copyright 2010, Texas Instruments Incorporated
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